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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-375-pinctrl.txt16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
20 mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
21 mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
24 mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
25 mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
46 mpp30 30 gpio, ge1(txd0), spi1(cs0)
47 mpp31 31 gpio, ge1(txd1), spi1(mosi)
48 mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig)
49 mpp33 33 gpio, ge1(txd3), spi1(miso)
[all …]
H A Dmarvell,armada-370-pinctrl.txt21 mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
28 sata1(prsnt), spi1(cs1)
29 mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
33 mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
35 mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
44 mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
45 mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
47 mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
71 mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
73 mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
[all …]
H A Dmarvell,armada-xp-pinctrl.txt34 mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13)
35 mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15)
37 mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16)
38 mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17)
62 spi1(cs1)
64 pcie(clkreq1), spi1(cs2)
67 spi1(cs3)
69 dram(bat), spi1(cs4)
71 spi1(cs5), dram(vttctrl)
73 spi1(cs6)
[all …]
H A Dmarvell,dove-pinctrl.txt24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
26 mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
27 mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
44 mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
46 mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
48 mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
50 mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
H A Dmarvell,armada-38x-pinctrl.txt59 mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0)
61 mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), n…
73 mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd)
74 mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
75 mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd)
76 mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(…
77 mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
H A Dmarvell,armada-39x-pinctrl.txt60 mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl)
62 mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
77 mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd)
78 mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
79 mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd)
80 mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
81 mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-375.c25 MPP_FUNCTION(0x3, "spi1", "cs1"),
31 MPP_FUNCTION(0x3, "spi1", "mosi"),
40 MPP_FUNCTION(0x6, "spi1", "mosi")),
48 MPP_FUNCTION(0x6, "spi1", "miso")),
53 MPP_FUNCTION(0x3, "spi1", "miso"),
59 MPP_FUNCTION(0x3, "spi1", "cs2"),
61 MPP_FUNCTION(0x6, "spi1", "miso")),
79 MPP_FUNCTION(0x3, "spi1", "cs0"),
84 MPP_FUNCTION(0x3, "spi1", "sck"),
91 MPP_FUNCTION(0x6, "spi1", "sck")),
[all …]
H A Dpinctrl-armada-cp110.c124 MPP_FUNCTION(5, "spi1", "csn1"),
134 MPP_FUNCTION(5, "spi1", "csn0"),
145 MPP_FUNCTION(5, "spi1", "mosi"),
153 MPP_FUNCTION(5, "spi1", "miso"),
161 MPP_FUNCTION(5, "spi1", "clk"),
170 MPP_FUNCTION(3, "spi1", "csn1"),
176 MPP_FUNCTION(3, "spi1", "miso"),
183 MPP_FUNCTION(3, "spi1", "csn0"),
192 MPP_FUNCTION(3, "spi1", "mosi"),
199 MPP_FUNCTION(3, "spi1", "clk"),
[all …]
H A Dpinctrl-armada-370.c42 MPP_FUNCTION(0x4, "spi1", "sck"),
80 MPP_FUNCTION(0x6, "spi1", "cs1")),
86 MPP_FUNCTION(0x4, "spi1", "cs0"),
100 MPP_FUNCTION(0x4, "spi1", "mosi"),
107 MPP_FUNCTION(0x4, "spi1", "miso"),
144 MPP_FUNCTION(0x4, "spi1", "mosi")),
149 MPP_FUNCTION(0x4, "spi1", "cs0")),
159 MPP_FUNCTION(0x4, "spi1", "miso")),
261 MPP_FUNCTION(0x4, "spi1", "cs0"),
268 MPP_FUNCTION(0x4, "spi1", "miso"),
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dk210-fpioa.h36 #define K210_PCF_CLK_SPI1 22 /* Clock SPI1 */
84 #define K210_PCF_SPI1_D0 70 /* SPI1 Data 0 */
85 #define K210_PCF_SPI1_D1 71 /* SPI1 Data 1 */
86 #define K210_PCF_SPI1_D2 72 /* SPI1 Data 2 */
87 #define K210_PCF_SPI1_D3 73 /* SPI1 Data 3 */
88 #define K210_PCF_SPI1_D4 74 /* SPI1 Data 4 */
89 #define K210_PCF_SPI1_D5 75 /* SPI1 Data 5 */
90 #define K210_PCF_SPI1_D6 76 /* SPI1 Data 6 */
91 #define K210_PCF_SPI1_D7 77 /* SPI1 Data 7 */
92 #define K210_PCF_SPI1_SS0 78 /* SPI1 Chip Select 0 */
[all …]
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-nezha.dts230 "pin24 [gpio16/spi1-ce0]",
231 "pin23 [gpio15/spi1-clk]",
232 "pin19 [gpio12/spi1-mosi]",
233 "pin21 [gpio13/spi1-miso]",
234 "pin27 [gpio18/spi1-hold]",
235 "pin29 [gpio20/spi1-wp]",
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq5-pins.dtsi65 spi1_pins: spi1-pins {
66 function = "spi1";
69 spi1_slave_pins: spi1-slave-pins {
70 function = "spi1";
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-suniv-f1c100s.c38 SUNXI_FUNCTION(0x6, "spi1")), /* CS */
45 SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
53 SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
61 SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
70 SUNXI_FUNCTION(0x6, "spi1")), /* CS */
78 SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
86 SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
94 SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
312 SUNXI_FUNCTION(0x4, "spi1"), /* CS */
319 SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-dhcor-som.dtsi58 * DHCOM SPI1 interface or accessing the SPI bootflash. Both using
59 * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
68 spi1-switch-hog {
72 line-name = "spi1-switch";
245 pinctrl_spi1_switch: spi1-switch-grp {
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-pxs3-ref.dts31 spi1 = &spi1;
54 &spi1 {
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc770-xm010.dts19 spi1 = &spi1;
103 &spi1 {
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-db-88f6820-amc.dts25 spi1 = &spi1;
124 &spi1 {
/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pinctrl.dtsi154 pinctrl_spi1: spi1 {
155 groups = "spi1";
156 function = "spi1";
/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9131-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
H A Dcn9132-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
H A Dcn9130-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
H A Dcn9132-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
H A Dcn9131-db.dts14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
/linux/arch/powerpc/platforms/83xx/
H A Dmpc832x_rdb.c169 par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */ in mpc832x_spi_init()
170 par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */ in mpc832x_spi_init()
171 par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */ in mpc832x_spi_init()
172 par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */ in mpc832x_spi_init()

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