Home
last modified time | relevance | path

Searched +full:spi0 +full:- +full:pins (Results 1 – 25 of 283) sorted by relevance

12345678910>>...12

/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
19 name pins functions
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
57 mpp36 36 gpio, spi0(mosi)
58 mpp37 37 gpio, spi0(miso)
59 mpp38 38 gpio, spi0(sck)
[all …]
H A Dtoshiba,visconti-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
18 - toshiba,tmpv7708-pinctrl
24 - $ref: pinctrl.yaml#
27 - compatible
28 - reg
31 '-pins$':
[all …]
H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
20 mpp4 4 gpio, vdd(cpu-pd)
27 mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
34 spi0(cs2)
36 spi0(cs3)
53 mpp32 32 gpio, spi0(cs0)
[all …]
H A Dmarvell,armada-38x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
30 mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
31 mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pci…
32 mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq)
33 mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
[all …]
H A Dmediatek,mt7986-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7986 Pin controller is used to control SoC pins.
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
25 reg-names:
27 - const: gpio
[all …]
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
33 mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
34 mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
35 mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
36 mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck)
[all …]
H A Dmarvell,armada-375-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
20 mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
21 mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
24 mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
[all …]
H A Dmediatek,mt7981-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek's MT7981 Pin controller is used to control SoC pins.
18 - mediatek,mt7981-pinctrl
24 reg-names:
26 - const: gpio
27 - const: iocfg_rt
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-iot2050-arduino-connector.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2023
13 pinctrl-names =
15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
21 "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
[all …]
/linux/arch/arm64/boot/dts/toshiba/
H A Dtmpv7708_pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 spi0_pins: spi0-pins {
5 function = "spi0";
8 spi1_pins: spi1-pins {
12 spi2_pins: spi2-pins {
16 spi3_pins: spi3-pins {
20 spi4_pins: spi4-pins {
24 spi5_pins: spi5-pins {
28 spi6_pins: spi6-pins {
32 uart0_pins: uart0-pins {
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-q5xr5.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
24 #address-cells = <1>;
25 #size-cells = <1>;
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <18432000>;
34 clock-frequency = <32768>;
38 clock-frequency = <18432000>;
51 compatible = "cfi-flash";
52 #address-cells = <1>;
[all …]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq6h-pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
20 // TODO: use pinctrl-single,bias-pullup
21 // TODO: use pinctrl-single,bias-pulldown
22 // TODO: use pinctrl-single,drive-strength
23 // TODO: use pinctrl-single,input-schmitt
25 i2c0_pins: i2c0-pins {
26 pinctrl-single,pins = <
31 i2c1_pins: i2c1-pins {
[all …]
H A Deyeq5-pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 timer0_pins: timer0-pins {
11 pins = "PA0", "PA1";
13 timer1_pins: timer1-pins {
15 pins = "PA2", "PA3";
17 timer2_pins: timer2-pins {
19 pins = "PA4", "PA5";
21 pps0_pins: pps0-pin {
23 pins = "PA4";
25 pps1_pins: pps1-pin {
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4018-ap120c-ac.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
8 model = "ALFA Network AP120C-AC";
9 compatible = "alfa-network,ap120c-ac", "qcom,ipq4018";
16 stdout-path = "serial0:115200n8";
20 compatible = "gpio-keys";
22 key-reset {
31 i2c0_pins: i2c0-state {
[all …]
H A Dqcom-ipq4019-ap.dk04.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
27 serial_0_pins: serial0-state {
28 pins = "gpio16", "gpio17";
30 bias-disable;
33 serial_1_pins: serial1-state {
[all …]
H A Dqcom-ipq4019-ap.dk01.1.dtsi17 #include <dt-bindings/gpio/gpio.h>
18 #include "qcom-ipq4019.dtsi"
21 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
28 stdout-path = "serial0:115200n8";
37 serial_pins: serial-state {
38 pins = "gpio60", "gpio61";
40 bias-disable;
43 spi_0_pins: spi-0-state {
44 spi0-pins {
45 pins = "gpio55", "gpio56", "gpio57";
[all …]
H A Dqcom-ipq4018-jalapeno.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
14 mdio_pins: mdio-state {
15 mdio-pins {
16 pins = "gpio53";
18 bias-pull-up;
21 mdc-pins {
22 pins = "gpio52";
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
[all …]
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm730-kudo.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
34 spi0 = &spi0;
41 stdout-path = &serial3;
48 iio-hwmon {
49 compatible = "iio-hwmon";
50 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
55 compatible = "nuvoton,npcm750-jtag-master";
[all …]
/linux/arch/riscv/boot/dts/thead/
H A Dth1520-lichee-pi-4a.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "th1520-lichee-module-4a.dtsi"
10 compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
25 spi0 = &spi0;
29 stdout-path = "serial0:115200n8";
34 uart0_pins: uart0-0 {
35 tx-pins {
36 pins = "UART0_TXD";
38 bias-disable;
39 drive-strength = <3>;
[all …]
/linux/Documentation/driver-api/
H A Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
23 can control PINs. It may be able to multiplex, bias, set load capacitance,
24 set drive strength, etc. for individual pins or groups of pins.
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
30 be sparse - i.e. there may be gaps in the space with numbers where no
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-rock960.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-rock960.dtsi"
14 stdout-path = "serial2:1500000n8";
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>,
24 user_led1: led-1 {
27 linux,default-trigger = "heartbeat";
30 user_led2: led-2 {
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-370.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include "armada-370-xp.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
31 compatible = "marvell,armada370-mbus", "simple-bus";
39 compatible = "marvell,armada-370-pcie";
43 #address-cells = <3>;
[all …]

12345678910>>...12