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/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-slave-mt27xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Slave controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - mediatek,mt2712-spi-slave
19 - mediatek,mt8195-spi-slave
30 clock-names:
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H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
21 Requirements to SPI slave nodes:
23 - There can be only one slave device.
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H A Dspi-sunplus-sp7021.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/spi-sunplus-sp7021.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus sp7021 SPI controller
11 - $ref: spi-controller.yaml
14 - Li-hao Kuo <lhjeff911@gmail.com>
19 - sunplus,sp7021-spi
23 - description: the SPI master registers
24 - description: the SPI slave registers
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H A Dspi-davinci.txt1 Davinci SPI controller device bindings
4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
10 address on the SPI bus. Should be set to 1.
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
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H A Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
17 for devices other than SPI NOR flash due to limited transfer
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H A Dmarvell,mmp2-ssp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/marvell,mmp2-ssp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: PXA2xx SSP SPI Controller
11 - Lubomir Rintel <lkundrak@v3.sk>
16 - marvell,mmp2-ssp
17 - mrvl,ce4100-ssp
18 - mvrl,pxa168-ssp
19 - mrvl,pxa25x-ssp
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/linux/drivers/base/regmap/
H A Dregmap-spi-avmm.c1 // SPDX-License-Identifier: GPL-2.0
3 // Register map access API - SPI AVMM support
5 // Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
9 #include <linux/spi/spi.h>
13 * This driver implements the regmap operations for a generic SPI
14 * master to access the registers of the spi slave chip which has an
17 * The "SPI slave to Avalon Master Bridge" (spi-avmm) IP should be integrated
18 * in the spi slave chip. The IP acts as a bridge to convert encoded streams of
20 * order to issue register access requests to the slave chip, the host should
28 * Chapter "SPI Slave/JTAG to Avalon Master Bridge Cores" is a general
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/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,fpga-slave-serial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
14 over what is referred to as slave serial interface.The slave serial link is
15 not technically SPI, and might require extra circuits in order to play nicely
16 with other SPI slaves on the same bus.
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H A Dlattice-machxo2-spi.txt1 Lattice MachXO2 Slave SPI FPGA Manager
4 'slave SPI' interface.
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
21 spi1: spi@2000 {
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H A Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
14 have Slave Serial Peripheral Interface. Only full reconfiguration is
23 - lattice,sysconfig-ecp5
28 program-gpios:
34 init-gpios:
40 done-gpios:
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/linux/drivers/spi/
H A Dspi-bitbang-txrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * simple SPI master driver. Two do polled word-at-a-time I/O:
6 * - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](),
7 * expanding the per-word routines from the inline templates below.
9 * - Drivers for controllers resembling bare shift registers. Provide
15 * - Drivers leveraging smarter hardware, with fifos or DMA; or for half
36 * A non-inlined routine would call bitbang_txrx_*() routines. The
49 bitbang_txrx_be_cpha0(struct spi_device *spi, in bitbang_txrx_be_cpha0() argument
55 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; in bitbang_txrx_be_cpha0()
57 for (word <<= (32 - bits); likely(bits); bits--) { in bitbang_txrx_be_cpha0()
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H A Dspi-slave-time.c2 * SPI slave handler reporting uptime at reception of previous SPI message
4 * This SPI slave handler sends the time of reception of the last SPI message
5 * as two 32-bit unsigned integers in binary format and in network byte order,
9 * Copyright (C) 2016-2017 Glider bvba
15 * Usage (assuming /dev/spidev2.0 corresponds to the SPI master on the remote
18 * # spidev_test -D /dev/spidev2.0 -p dummy-8B
19 * spi mode: 0x0
30 #include <linux/spi/spi.h>
34 struct spi_device *spi; member
48 ret = priv->msg.status; in spi_slave_time_complete()
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H A Dspi-slave-system-control.c2 * SPI slave handler controlling system state
4 * This SPI slave handler allows remote control of system reboot, power off,
7 * Copyright (C) 2016-2017 Glider bvba
13 * Usage (assuming /dev/spidev2.0 corresponds to the SPI master on the remote
20 * # spidev_test -D /dev/spidev2.0 -p $suspend # or $reboot, $poweroff, $halt
27 #include <linux/spi/spi.h>
30 * The numbers are chosen to display something human-readable on two 7-segment
39 struct spi_device *spi; member
55 if (priv->msg.status) in spi_slave_system_control_complete()
58 cmd = be16_to_cpu(priv->cmd); in spi_slave_system_control_complete()
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H A Dspi-slave-mt27xx.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
12 #include <linux/spi/spi.h>
90 { .compatible = "mediatek,mt2712-spi-slave",
92 { .compatible = "mediatek,mt8195-spi-slave",
102 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
105 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
112 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
115 writel(reg_val, mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
120 if (wait_for_completion_interruptible(&mdata->xfer_done) || in mtk_spi_slave_wait_for_completion()
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H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (host and target mode)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
22 #include <linux/spi/spi.h>
25 #define CDNS_SPI_NAME "cdns-spi"
37 #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
42 * SPI Configuration Register bit Masks
45 * of the SPI controller
50 #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
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/linux/drivers/fpga/
H A Dmachxo2-spi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Lattice MachXO2 Slave SPI Driver
5 * Manage Lattice FPGA firmware that is loaded over SPI using
6 * the slave serial configuration interface.
12 #include <linux/fpga/fpga-mgr.h>
16 #include <linux/spi/spi.h>
18 /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
29 * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
30 * Sheet' sysCONFIG Port Timing Specifications (3-36)
66 static int get_status(struct spi_device *spi, unsigned long *status) in get_status() argument
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H A Dlattice-sysconfig-spi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Lattice FPGA programming over slave SPI sysCONFIG interface.
7 #include <linux/spi/spi.h>
9 #include "lattice-sysconfig.h"
17 struct spi_device *spi = to_spi_device(priv->dev); in sysconfig_spi_cmd_transfer() local
19 return spi_write_then_read(spi, tx_buf, tx_len, rx_buf, rx_len); in sysconfig_spi_cmd_transfer()
25 struct spi_device *spi = to_spi_device(priv->dev); in sysconfig_spi_bitstream_burst_init() local
36 return -ENOMEM; in sysconfig_spi_bitstream_burst_init()
45 * Lock SPI bus for exclusive usage until FPGA programming is done. in sysconfig_spi_bitstream_burst_init()
46 * SPI bus will be released in sysconfig_spi_bitstream_burst_complete(). in sysconfig_spi_bitstream_burst_init()
[all …]
/linux/include/linux/amba/
H A Dpl022.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2008-2009 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
31 * enum ssp_interface - interfaces allowed for this SSP Controller
48 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
56 * enum ssp_clock_params - clock parameters, to set SSP clock at a
65 * enum ssp_rx_endian - endianess of Rx FIFO Data
74 * enum ssp_tx_endian - endianess of Tx FIFO Data
82 * enum ssp_data_size - number of bits in one data element
98 * enum ssp_mode - SSP mode of operation (Communication modes)
[all …]
/linux/drivers/nfc/nfcmrvl/
H A Dspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell NFC-over-SPI driver: SPI interface related functions
14 #include <linux/spi/spi.h>
21 struct spi_device *spi; member
36 if (test_and_clear_bit(SPI_WAIT_HANDSHAKE, &drv_data->flags)) { in nfcmrvl_spi_int_irq_thread_fn()
37 complete(&drv_data->handshake_completion); in nfcmrvl_spi_int_irq_thread_fn()
41 /* Normal case, SPI_INT deasserted by slave to trigger a master read */ in nfcmrvl_spi_int_irq_thread_fn()
43 skb = nci_spi_read(drv_data->nci_spi); in nfcmrvl_spi_int_irq_thread_fn()
45 nfc_err(&drv_data->spi->dev, "failed to read spi packet"); in nfcmrvl_spi_int_irq_thread_fn()
49 if (nfcmrvl_nci_recv_frame(drv_data->priv, skb) < 0) in nfcmrvl_spi_int_irq_thread_fn()
[all …]
/linux/drivers/iio/accel/
H A Dadxl367_spi.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/spi/spi.h>
21 struct spi_device *spi; member
46 st->fifo_xfer[1].rx_buf = fifo_buf; in adxl367_read_fifo()
47 st->fifo_xfer[1].len = fifo_entries * sizeof(*fifo_buf); in adxl367_read_fifo()
49 return spi_sync(st->spi, &st->fifo_msg); in adxl367_read_fifo()
58 st->reg_read_tx_buf[1] = reg; in adxl367_read()
59 st->reg_read_xfer[1].rx_buf = val_buf; in adxl367_read()
60 st->reg_read_xfer[1].len = val_size; in adxl367_read()
62 return spi_sync(st->spi, &st->reg_read_msg); in adxl367_read()
[all …]
/linux/drivers/net/wireless/microchip/wilc1000/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 This provides Wi-FI over an SDIO or SPI interface, and
19 the 1-bit/4-bit SD transfer mode at the clock range of 0-50 MHz.
26 tristate "Atmel WILC1000 SPI (WiFi only)"
27 depends on CFG80211 && INET && SPI
32 This module adds support for the SPI interface of adapters using
34 Interface (SPI) that operates as a SPI slave. This SPI interface can
35 be used for control and for serial I/O of 802.11 data. The SPI is a
36 full-duplex slave synchronous serial interface that is available
38 VDDIO. Select this if your platform is using the SPI bus.
[all …]
/linux/include/linux/platform_data/
H A Dspi-s3c64xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * struct s3c64xx_spi_csinfo - ChipSelect description
17 * @fb_delay: Slave specific feedback delay.
18 * Refer to FB_CLK_SEL register definition in SPI chapter.
20 * This is per SPI-Slave Chipselect information.
29 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @cfg_gpio: Configure pins for this SPI controller.
44 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
46 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
49 * Call this from machine init code for each SPI Controller that
/linux/Documentation/devicetree/bindings/misc/
H A Dolpc,xo1.75-ec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/misc/olpc,xo1.75-ec.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: OLPC XO-1.75 Embedded Controller
11 This binding describes the Embedded Controller acting as a SPI bus master
12 on a OLPC XO-1.75 laptop computer.
14 The embedded controller requires the SPI controller driver to signal
17 "ready-gpios" property of the SSP binding as documented in:
18 <Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dqca,qca7000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The QCA7000 is a serial-to-powerline bridge with a host interface which could
14 be configured either as SPI or UART slave. This configuration is done by
17 (a) Ethernet over SPI
19 In order to use the QCA7000 as SPI device it must be defined as a child of a
20 SPI master in the device tree.
24 In order to use the QCA7000 as UART slave it must be defined as a child of a
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-tarragon-slave.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
5 #include "imx6ull-tarragon-common.dtsi"
8 model = "chargebyte Tarragon Slave";
9 compatible = "chargebyte,imx6ull-tarragon-slave", "fsl,imx6ull";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_qca700x_cp_int
22 interrupt-parent = <&gpio2>;
24 spi-cpha;
25 spi-cpol;
26 spi-max-frequency = <12000000>;

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