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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt1024qds.dts35 /include/ "t102xsi-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
44 reserved-memory {
45 #address-cells = <2>;
46 #size-cells = <2>;
47 ranges;
49 bman_fbpr: bman-fbpr {
54 qman_fqd: qman-fqd {
[all …]
H A Dkmcoge4.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
11 /include/ "p2041si-pre.dtsi"
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&mpic>;
24 reserved-memory {
25 #address-cells = <2>;
26 #size-cells = <2>;
27 ranges;
29 bman_fbpr: bman-fbpr {
[all …]
H A Dt208xqds.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
45 ranges;
47 bman_fbpr: bman-fbpr {
51 qman_fqd: qman-fqd {
[all …]
H A Dt104xd4rdb.dtsi36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
39 ranges;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
57 ranges = <0 0 0xf 0xe8000000 0x08000000
62 #address-cells = <1>;
63 #size-cells = <1>;
[all …]
H A Dt1024rdb.dts35 /include/ "t102xsi-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
51 ranges;
53 bman_fbpr: bman-fbpr {
58 qman_fqd: qman-fqd {
[all …]
H A Dp1020rdb-pd.dts2 * P1020 RDB-PD Device Tree Source (32-bit address map)
35 /include/ "p1020si-pre.dtsi"
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
58 bank-width = <2>;
59 device-width = <1>;
[all …]
H A Dp2020rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009-2012 Freescale Semiconductor Inc.
8 /include/ "p2020si-pre.dtsi"
32 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
[all …]
H A Dmvme2500.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
11 /include/ "p2020si-pre.dtsi"
29 ranges = <0x0 0 0xffe00000 0x100000>;
65 spi0: spi@7000 {
66 fsl,espi-num-chipselects = <2>;
69 compatible = "atmel,at25df641", "jedec,spi-nor";
71 spi-max-frequency = <10000000>;
74 compatible = "atmel,at25df641", "jedec,spi-nor";
76 spi-max-frequency = <10000000>;
[all …]
H A Dp1021mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "p1021si-pre.dtsi"
26 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "fsl,p1021-fcm-nand",
35 "fsl,elbc-fcm-nand";
40 /* 1MB for u-boot Bootloader Image */
42 label = "NAND (RO) U-Boot Image";
43 read-only;
[all …]
H A Dt104xrdb.dtsi4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
45 ranges;
47 bman_fbpr: bman-fbpr {
51 qman_fqd: qman-fqd {
55 qman_pfdr: qman-pfdr {
63 ranges = <0 0 0xf 0xe8000000 0x08000000
68 #address-cells = <1>;
[all …]
H A Dp1022rdk.dts2 * P1022 RDK 32-bit Physical Address Map Device Tree Source
35 /include/ "p1022si-pre.dtsi"
50 ranges = <0x0 0x0 0xffe00000 0x100000>;
56 /* MCLK source is a stand-alone oscillator */
57 clock-frequency = <12288000>;
85 spi@7000 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "spansion,m25p80", "jedec,spi-no
[all...]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmarvell,ap806-gicp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
13 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
16 into GIC SPI interrupts.
20 const: marvell,ap806-gicp
25 marvell,spi-ranges:
26 description: Tuples of GIC SPI interrupt ranges available for this GICP
[all …]
H A Dmarvell,gicp.txt2 -----------------------
4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
11 - compatible: Must be "marvell,ap806-gicp"
13 - reg: Must be the address and size of the GICP SPI registers
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
18 - msi-controller: indicates that this is an MSI controller
22 gicp_spi: gicp-spi@3f0040 {
23 compatible = "marvell,ap806-gicp";
25 marvell,spi-ranges = <64 64>, <288 64>;
[all …]
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov920.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
[all …]
H A Dexynosautov9.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a76-pmu";
[all …]
H A Dexynos8895.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
8 #include <dt-bindings/clock/samsung,exynos8895.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <1>;
16 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
33 cpu-map {
67 compatible = "samsung,mongoose-m2";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-orion.txt1 Marvell Orion SPI device
4 - compatible : should be on of the following:
5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6 - "marvell,armada-370-spi", for the Armada 370 SoCs
7 - "marvell,armada-375-spi", for the Armada 375 SoCs
8 - "marvell,armada-380-spi", for the Armada 38x SoCs
9 - "marvell,armada-390-spi", for the Armada 39x SoCs
10 - "marvell,armada-xp-spi", for the Armada XP SoCs
11 - reg : offset and length of the register set for the device.
13 the SPI direct access mode that some of the Marvell SoCs support
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
30 gic: interrupt-controller@2561000 {
31 compatible = "arm,gic-400", "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include <dt-bindings/clock/google,gs101.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Datmel,sama5d2-flexcom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
13 The Microchip Flexcom is just a wrapper which embeds a SPI controller,
20 - const: atmel,sama5d2-flexcom
21 - items:
22 - enum:
23 - microchip,sam9x7-flexcom
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmmc-spi-slot.txt1 MMC/SD/SDIO slot directly connected to a SPI bus
7 - spi-max-frequency : maximum frequency for this device (Hz).
10 - voltage-ranges : two cells are required, first cell specifies minimum
12 Several ranges could be specified. If not provided, 3.2v..3.4v is assumed.
13 - gpios : may specify GPIOs in this order: Card-Detect GPIO,
14 Write-Protect GPIO. Note that this does not follow the
19 mmc-slot@0 {
20 compatible = "fsl,mpc8323rdb-mmc-slot",
21 "mmc-spi-slot";
25 voltage-ranges = <3300 3300>;
[all …]
H A Dmmc-spi-slot.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC/SD/SDIO slot directly connected to a SPI bus
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml
14 - $ref: /schemas/spi/spi-peripheral-props.yaml
17 The extra properties used by an mmc connected via SPI.
21 const: mmc-spi-slot
[all …]
/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep93xx-edb9302.dts1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
5 /dts-v1/;
9 #address-cells = <1>;
10 #size-cells = <1>;
27 compatible = "audio-graph-card2";
33 compatible = "gpio-leds";
34 led-0 {
37 linux,default-trigger = "heartbeat";
41 led-1 {
55 compatible = "cfi-flash";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,sa8255p-geni-se-qup.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Praveen Talari <quic_ptalari@quicinc.com>
15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial
22 const: qcom,sa8255p-geni-se-qup
28 "#address-cells":
31 "#size-cells":
34 ranges: true
[all …]

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