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Searched +full:spi +full:- +full:ns2 +full:- +full:qspi (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dbrcm,spi-bcm-qspi.txt1 Broadcom SPI controller
3 The Broadcom SPI controller is a SPI master found on various SOCs, including
4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
6 MSPI : SPI master controller can read and write to a SPI slave device
7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
9 io with 3-byte and 4-byte addressing support.
14 use SPI protocol.
18 - #address-cells:
19 Must be <1>, as required by generic SPI binding.
21 - #size-cells:
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H A Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brc
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2-svk.dts33 /dts-v1/;
35 #include "ns2.dtsi"
38 model = "Broadcom NS2 SVK";
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
113 spi-max-frequency = <5000000>;
114 spi-cpha;
115 spi-cpol;
117 pl022,slave-tx-disable = <0>;
118 pl022,com-mode = <0>;
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H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
39 compatible = "brcm,ns2";
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
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H A Dns2-xmc.dts33 /dts-v1/;
35 #include "ns2.dtsi"
38 model = "Broadcom NS2 XMC";
39 compatible = "brcm,ns2-xmc", "brcm,ns2";
46 stdout-path = "serial0:115200n8";
70 gphy0: eth-phy@10 {
80 nand-ecc-mode = "hw";
81 nand-ecc-strength = <8>;
82 nand-ecc-step-size = <512>;
83 nand-bus-width = <16>;
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