Home
last modified time | relevance | path

Searched +full:spi +full:- +full:nor (Results 1 – 25 of 702) sorted by relevance

12345678910>>...29

/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
[all …]
H A Dspi-mtk-nor.txt1 * Serial NOR flash controller for MediaTek ARM SoCs
4 - compatible: For mt8173, compatible should be "mediatek,mt8173-nor",
6 For every other SoC, should contain both the SoC-specific compatible
7 string and "mediatek,mt8173-nor".
9 "mediatek,mt2701-nor", "mediatek,mt8173-nor"
10 "mediatek,mt2712-nor", "mediatek,mt8173-nor"
11 "mediatek,mt7622-nor", "mediatek,mt8173-nor"
12 "mediatek,mt7623-nor", "mediatek,mt8173-nor"
13 "mediatek,mt7629-nor", "mediatek,mt8173-nor"
14 "mediatek,mt8173-nor"
[all …]
H A Dcdns,xspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2020-21 Cadence
4 ---
5 $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Parshuram Thombare <pthombar@cadence.com>
14 The XSPI controller allows SPI protocol communication in
16 read/write access to slaves such as SPI-NOR flash.
21 - cdns,xspi-nor
22 - marvell,cn10-xspi-nor
[all …]
H A Daspeed,ast2600-fmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
11 - Cédric Le Goater <clg@kaod.org>
15 SPI) of the AST2400, AST2500 and AST2600 SOCs.
18 - $ref: spi-controller.yaml#
23 - aspeed,ast2600-fmc
24 - aspeed,ast2600-spi
[all …]
H A Dspi-fsl-qspi.txt4 - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
5 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
6 "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
8 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
9 - reg : the first contains the register location and length,
11 - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
12 - interrupts : Should contain the interrupt for the device
13 - clocks : The clocks needed by the QuadSPI controller
14 - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
16 Required SPI slave node properties:
[all …]
H A Dcadence-quadspi.txt1 * Cadence Quad SPI controller
4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
9 - reg : Contains two entries, each of which is a tuple consisting of a
13 - interrupts : Unit interrupt specifier for the controller interrupt.
14 - clocks : phandle to the Quad SPI clock.
15 - cdns,fifo-depth : Size of the data FIFO in words.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dhisilicon,fmc-spi-nor.txt1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
[all …]
H A Djedec,spi-nor.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
13 - $ref: mtd.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
19 - items:
20 - pattern: "^((((micron|spansion|st),)?\
[all …]
H A Daspeed-smc.txt2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
[all …]
H A Djedec,spi-nor.txt1 * SPI NOR flash: ST M25Pxx (and similar) serial flash chips
4 - #address-cells, #size-cells : Must be present if the device has sub-nodes
6 - compatible : May include a device-specific string consisting of the
9 Must also include "jedec,spi-nor" for any SPI NOR flash that can
53 m25p05-nonjedec
54 m25p10-nonjedec
55 m25p20-nonjedec
56 m25p40-nonjedec
57 m25p80-nonjedec
58 m25p16-nonjedec
[all …]
H A Dnxp-spifi.txt1 * NXP SPI Flash Interface (SPIFI)
3 NXP SPIFI is a specialized SPI interface for serial Flash devices.
4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
10 - compatible : Should be "nxp,lpc1773-spifi"
11 - reg : the first contains the register location and length,
13 - reg-names: Should contain the reg names "spifi" and "flash"
14 - interrupts : Should contain the interrupt for the device
15 - clocks : The clocks needed by the SPIFI controller
16 - clock-names : Should contain the clock names "spifi" and "reg"
19 - resets : phandle + reset specifier
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
21 sys_mclk: clock-mclk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
27 reg_3p3v: regulator-3p3v {
28 compatible = "regulator-fixed";
[all …]
H A Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls2088a.dtsi"
17 compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
25 stdout-path = "serial1:115200n8";
33 compatible = "jedec,spi-nor";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 spi-max-frequency = <3000000>;
51 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
[all …]
H A Dp1024rdb.dtsi2 * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
[all …]
H A Dp1022ds.dtsi2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
47 read-only;
[all …]
H A Dp1020rdb-pd.dts2 * P1020 RDB-PD Device Tree Source (32-bit address map)
13 * * Neither the name of Freescale Semiconductor nor the
35 /include/ "p1020si-pre.dtsi"
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
47 /* NOR, NAND flash, L2 switch and CPLD */
53 nor@0,0 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
[all …]
H A Dp2020rdb-pc.dtsi2 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
[all …]
H A Dp1010rdb.dtsi2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
47 label = "NOR DTB Image";
53 label = "NOR Linux Kernel Image";
[all …]
H A Dp1021rdb-pc.dtsi2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
[all …]
H A Dc293pcie.dts13 * * Neither the name of Freescale Semiconductor nor the
35 /include/ "c293si-pre.dtsi"
45 ifc: memory-controller@fffe1e000 {
74 nor@0,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "cfi-flash";
79 bank-width = <2>;
80 device-width = <1>;
85 label = "NOR DTB Image";
[all …]
H A Dp2020rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009-2012 Freescale Semiconductor Inc.
8 /include/ "p2020si-pre.dtsi"
31 /* NOR and NAND Flashes */
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drenesas,rpc-if.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
19 - if it contains "jedec,spi-nor", then SPI is used;
20 - if it contains "cfi-flash", then HyperFlash is used.
[all …]

12345678910>>...29