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Searched +full:spi +full:- +full:cs +full:- +full:sck +full:- +full:delay (Results 1 – 23 of 23) sorted by relevance

/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
36 shunt-resistor = <1000>;
67 #address-cells = <2>;
68 #size-cells = <1>;
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/linux/Documentation/devicetree/bindings/spi/
H A Dfsl,dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,dspi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for Freescale DSPI controller
10 - Vladimir Oltean <olteanv@gmail.com>
13 See spi-peripheral-props.yaml for more info.
16 fsl,spi-cs-sck-delay:
19 Delay in nanoseconds between activating chip select and the start of
23 fsl,spi-sck-cs-delay:
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/linux/drivers/spi/
H A Dspi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI host driver using generic bitbanged GPIO
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
17 #include <linux/spi/spi_gpio.h>
20 * This bitbanging SPI host driver should help make systems usable
21 * when a native hardware SPI engine is not available, perhaps because
25 * platform_device->driver_data ... points to spi_gpio
27 * spi->controller_state ... reserved for bitbang framework code
29 * spi->controller->dev.driver_data ... points to spi_gpio->bitbang
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H A Dspi-bcm-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
9 #include <linux/delay.h>
21 #include <linux/spi/spi.h>
22 #include <linux/mtd/spi-nor.h>
25 #include "spi-bcm-qspi.h"
153 /* stop at end of spi_transfer if delay */
165 /* events that make us deassert CS */
171 * to TXRAM and RXRAM when used as 32-bit registers respectively
257 return qspi->bspi_mode; in has_bspi()
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H A Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
32 #include <linux/platform_data/spi-omap2-mcspi.h>
49 /* per-channel banks, 0x14 bytes each, first is: */
56 /* per-register bitmasks: */
92 /* We have 2 DMA channels per CS, one for RX and one for TX */
117 struct list_head cs; member
155 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
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/linux/Documentation/iio/
H A Dad4000.rst1 .. SPDX-License-Identifier: GPL-2.0-only
41 * `AD7988-1 <https://www.analog.com/AD7988-1>`_
42 * `AD7988-5 <https://www.analog.com/AD7988-5>`_
45 ------------------
47 Devices of the AD4000 series can be connected to the SPI host controller in a
50 CS mode, 3-wire turbo mode
53 Datasheet "3-wire" mode is what most resembles standard SPI connection which,
54 for these devices, comprises of connecting the controller CS line to device CNV
55 pin and other SPI lines as usual. This configuration is (misleadingly) called
56 "CS Mode, 3-Wire Turbo Mode" connection in datasheets.
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/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-bk4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
15 stdout-path = &uart1;
23 audio_ext: oscillator-audio {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <24576000>;
29 enet_ext: oscillator-ethernet {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
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H A Dvf610-zii-dev-rev-c.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "vf610-zii-dev.dtsi"
11 compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
13 mdio-mux {
14 compatible = "mdio-mux-gpio";
15 pinctrl-0 = <&pinctrl_mdio_mux>;
16 pinctrl-names = "default";
20 mdio-parent-bus = <&mdio1>;
21 #address-cells = <1>;
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/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
25 regulator-min-microvolt = <3300000>;
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/linux/Documentation/spi/
H A Dspi-summary.rst2 Overview of Linux kernel SPI support
5 02-Feb-2012
7 What is SPI?
8 ------------
9 The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
12 standardization body. SPI uses a host/target configuration.
14 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
22 SPI hosts use a fourth "chip select" line to activate a given SPI target
24 in parallel. All SPI targets support chipselects; they are usually active
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/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
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H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = &uart0;
32 compatible = "gpio-keys";
34 button-wps {
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H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-zii-rdu1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/sound/fsl-imx-audmux.h>
12 compatible = "zii,imx51-rdu1", "fsl,imx51";
15 stdout-path = &uart1;
25 mdio-gpio0 = &mdio_gpio;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <26000000>;
36 compatible = "gpio-gate-clock";
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H A Dimx7d-sdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 /dts-v1/;
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
19 stdout-path = &uart1;
27 gpio-keys {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpio_keys>;
32 key-volume-up {
36 wakeup-source;
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H A Dimx6ul-14x14-evk.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/media/video-interfaces.h>
9 stdout-path = &uart1;
17 backlight_display: backlight-display {
18 compatible = "pwm-backlight";
20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>;
25 reg_1v5: regulator-1v5 {
26 compatible = "regulator-fixed";
27 regulator-name = "1v5";
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/linux/arch/mips/boot/dts/ingenic/
H A Dqi_lb60.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/iio/adc/ingenic,adc.h>
8 #include <dt-bindings/clock/ingenic,tcu.h>
9 #include <dt-bindings/input/input.h>
27 stdout-path = &uart0;
30 vcc: regulator-0 {
31 compatible = "regulator-fixed";
32 regulator-name = "vcc";
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/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-tx28.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 model = "Ka-Ro electronics TX28 module";
34 reg = <0x40000000 0>; /* will be filled in by U-Boot */
38 compatible = "w1-gpio";
43 reg_usb0_vbus: regulator-usb0-vbus {
44 compatible = "regulator-fixed";
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-ux500-samsung-gavini.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy Beam GT-I8530 also known as Gavini.
6 /dts-v1/;
7 #include "ste-db8500.dtsi"
8 #include "ste-ab8500.dtsi"
9 #include "ste-dbx5x0-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
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H A Ds5pv210-aries.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
32 reserved-memory {
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "shared-dma-pool";
39 no-map;
44 compatible = "shared-dma-pool";
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H A Dexynos4210-i9100.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm8250.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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