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/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
[all …]
H A Dnvidia,tegra114-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra114 SPI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - const: nvidia,tegra114-spi
17 - items:
18 - enum:
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
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/linux/drivers/spi/
H A Dspi-bcmbca-hsspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCMBCA High Speed SPI Controller driver
5 * Copyright 2000-2010 Broadcom Corporation
6 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright 2019-2022 Broadcom Ltd
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
23 #include <linux/spi/spi-mem.h>
99 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
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H A Dspi-loongson-core.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Loongson SPI Support
5 #include <linux/clk.h>
15 #include <linux/spi/spi.h>
17 #include "spi-loongson.h"
19 static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsigned char reg, in loongson_spi_write_reg() argument
22 writeb(data, spi->base + reg); in loongson_spi_write_reg()
25 static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigned char reg) in loongson_spi_read_reg() argument
27 return readb(spi->base + reg); in loongson_spi_read_reg()
30 static void loongson_spi_set_cs(struct spi_device *spi, bool en) in loongson_spi_set_cs() argument
[all …]
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
9 * SPI host mode controller driver, used in STMicroelectronics devices.
12 #include <linux/clk.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
54 /* SSC SPI Controller */
56 struct clk *clk; member
59 /* SSC SPI current transaction */
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
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H A Dspi-bcm63xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom BCM63xx SPI controller support
5 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
10 #include <linux/clk.h>
16 #include <linux/spi/spi.h>
23 /* BCM 6338/6348 SPI core */
25 #define SPI_6348_CMD 0x00 /* 16-bits register */
34 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
41 /* BCM 3368/6358/6262/6368 SPI core */
43 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
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H A Dspi-mpc512x-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC512x PSC in SPI mode driver.
7 * Hongjun Chen <hong-jun.chen@freescale.com>
22 #include <linux/clk.h>
23 #include <linux/spi/spi.h>
37 switch (mps->type) { \
39 struct mpc52xx_psc __iomem *psc = mps->psc; \
40 __ret = &psc->regname; \
44 struct mpc5125_psc __iomem *psc = mps->psc; \
45 __ret = &psc->regname; \
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H A Dspi-jcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * J-Core SPI controller driver
5 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
16 #include <linux/spi/spi.h>
17 #include <linux/clk.h>
52 } while (--timeout); in jcore_spi_wait()
54 return -EBUSY; in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program()
62 dev_err(hw->host->dev.parent, in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
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H A Dspi-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
13 #include <linux/clk.h>
21 #include <linux/spi/spi.h>
23 #define DRIVER_NAME "spi-mt7621"
65 static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi) in spidev_to_mt7621_spi() argument
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H A Dspi-bcm63xx-hsspi.c2 * Broadcom BCM63XX High Speed SPI Controller driver
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
23 #include <linux/spi/spi-mem.h>
24 #include <linux/mtd/spi-nor.h>
105 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
124 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) \
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H A Dspi-armada-3700.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Armada-3700 SPI controller driver
8 * Author: Romain Perier <romain.perier@free-electrons.com>
11 #include <linux/clk.h>
22 #include <linux/spi/spi.h>
30 /* SPI Register Offest */
104 struct clk *clk; member
118 return readl(a3700_spi->base + offset); in spireg_read()
123 writel(data, a3700_spi->base + offset); in spireg_write()
171 /* RX during address reception uses 4-pin */ in a3700_spi_pin_mode_set()
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H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
12 #include <linux/clk.h>
24 #include <linux/spi/spi-mem.h>
25 #include <linux/spi/spi.h>
27 #include "spi-dw.h"
34 struct clk *clk; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
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H A Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
13 #include <linux/spi/spi.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
61 * bit: |---3-------2-------1-------0
71 * The Designware SPI controller (referred to as master in the documentation)
74 * the SPI boot controller registers. the final chip select is an OR gate
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H A Dspi-ingenic.c1 // SPDX-License-Identifier: GPL-2.0
3 * SPI bus driver for the Ingenic SoCs
4 * Copyright (c) 2017-2021 Artur Rojek <contact@artur-rojek.eu>
5 * Copyright (c) 2017-2021 Paul Cercueil <paul@crapouillou.net>
9 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi.h>
64 struct clk *clk; member
77 return regmap_read_poll_timeout(priv->map, REG_SSISR, val, in spi_ingenic_wait()
82 static void spi_ingenic_set_cs(struct spi_device *spi, bool disable) in spi_ingenic_set_cs() argument
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H A Dspi-meson-spicc.c2 * Driver for Amlogic Meson SPI communication controller (SPICC)
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
19 #include <linux/spi/spi.h>
24 #include <linux/dma-mapping.h>
31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made
40 * - 64 bits per word
41 * - The transfer length in word must be multiples of the dma_burst_len, and
43 * into several SPI bursts by this driver
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H A Dspi-xlp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2003-2015 Broadcom Corporation
7 #include <linux/clk.h>
11 #include <linux/spi/spi.h>
14 /* SPI Configuration Register */
25 /* SPI Frequency Divider Register */
28 /* SPI Command Register */
37 /* SPI Status Register */
47 /* SPI Interrupt Enable Register */
55 /* SPI FIFO Threshold Register */
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H A Dspi-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Cirrus Logic EP93xx SPI controller.
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
11 * For more information about the SPI controller see documentation on Cirrus
17 #include <linux/clk.h>
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
31 #include <linux/spi/spi.h>
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H A Dspi-cavium-thunderx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cavium ThunderX SPI driver.
11 #include <linux/spi/spi.h>
13 #include "spi-cavium.h"
15 #define DRV_NAME "spi-thunderx"
22 struct device *dev = &pdev->dev; in thunderx_spi_probe()
29 return -ENOMEM; in thunderx_spi_probe()
41 p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); in thunderx_spi_probe()
42 if (!p->register_base) { in thunderx_spi_probe()
43 ret = -EINVAL; in thunderx_spi_probe()
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H A Dspi-stm32-qspi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
7 #include <linux/clk.h>
9 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
93 #define STM32_AUTOSUSPEND_DELAY -1
107 struct clk *clk; member
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
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H A Dspi-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/clk.h>
16 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi_bitbang.h>
22 #include <linux/platform_data/spi-davinci.h>
40 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
88 /* SPI Controller registers */
103 /* SPI Controller driver's private data. */
106 struct clk *clk; member
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
20 It features up to 8 serial digital interfaces (SPI or Manchester) and
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/linux/arch/mips/bcm63xx/
H A Dclk.c13 #include <linux/clk.h>
21 struct clk { struct
22 void (*set)(struct clk *, int); argument
31 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked() argument
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
37 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked() argument
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov920.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
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/linux/drivers/iio/adc/
H A Dstm32-dfsdm-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
24 #include "stm32-dfsdm.h"
27 * struct stm32_dfsdm_dev_data - DFSDM compatible configuration data
97 unsigned int spi_clk_out_div; /* SPI clkout divider value */
100 struct clk *clk; /* DFSDM clock */ member
101 struct clk *aclk; /* audio clock */
114 ret = clk_prepare_enable(priv->clk); in stm32_dfsdm_clk_prepare_enable()
115 if (ret || !priv->aclk) in stm32_dfsdm_clk_prepare_enable()
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