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/linux/drivers/pcmcia/
H A Dsoc_common.c4 integrated SOCs like the SA-11x0 and PXA2xx microprocessors.
71 printk(KERN_DEBUG "skt%u: %s: %pV", skt->nr, func, &vaf); in soc_pcmcia_debug()
89 if (!r->reg) in soc_pcmcia_regulator_set()
93 if (r->on == on) in soc_pcmcia_regulator_set()
97 ret = regulator_set_voltage(r->reg, v * 100000, v * 100000); in soc_pcmcia_regulator_set()
99 int vout = regulator_get_voltage(r->reg) / 100000; in soc_pcmcia_regulator_set()
101 dev_warn(&skt->socket.dev, in soc_pcmcia_regulator_set()
103 r == &skt->vcc ? "Vcc" : "Vpp", in soc_pcmcia_regulator_set()
107 ret = regulator_enable(r->reg); in soc_pcmcia_regulator_set()
109 ret = regulator_disable(r->reg); in soc_pcmcia_regulator_set()
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_port.c1 // SPDX-License-Identifier: GPL-2.0+
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
54 status->duplex = DUPLEX_HALF; in decode_sgmii_word()
59 status->link = !(lp_abil & ADVERTISE_RFAULT) && status->link; in decode_cl37_word()
[all …]
/linux/drivers/usb/dwc2/
H A Dhcd_queue.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
17 #include <linux/dma-mapping.h>
36 * dwc2_periodic_channel_available() - Checks that a channel is available for a
48 * non-periodic transactions in dwc2_periodic_channel_available()
53 num_channels = hsotg->params.host_channels; in dwc2_periodic_channel_available()
54 if ((hsotg->periodic_channels + hsotg->non_periodic_channels < in dwc2_periodic_channel_available()
55 num_channels) && (hsotg->periodic_channels < num_channels - 1)) { in dwc2_periodic_channel_available()
58 dev_dbg(hsotg->dev, in dwc2_periodic_channel_available()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
192 * struct dw_i2c_dev - private i2c-designware data
194 * @map: IO registers map
195 * @sysmap: System controller registers map
203 * @get_clk_rate_khz: callback to retrieve IP specific bus speed
225 * @rx_outstanding: current master-rx elements in tx fifo
228 * @ss_hcnt: standard speed HCNT value
229 * @ss_lcnt: standard speed LCNT value
230 * @fs_hcnt: fast speed HCNT value
231 * @fs_lcnt: fast speed LCNT value
[all …]
H A Di2c-designware-master.c1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #include "i2c-designware-core.h"
37 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
38 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
41 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
48 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
57 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
62 /* Set standard and fast speed dividers for high/low periods */ in i2c_dw_set_timings_master()
63 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
64 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
[all …]
H A Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
35 #include "i2c-designware-core.h"
65 "incorrect slave-transmitter mode configuration",
72 *val = readl(dev->base + reg); in dw_reg_read()
81 writel(val, dev->base + reg); in dw_reg_write()
90 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
99 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
108 *val = readw(dev->base + reg) | in dw_reg_read_word()
109 (readw(dev->base + reg + 2) << 16); in dw_reg_read_word()
118 writew(val, dev->base + reg); in dw_reg_write_word()
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux/usr/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 space-separated list of directories and files for building the
21 See <file:Documentation/driver-api/early-userspace/early_userspace_support.rst> for more details.
36 int "User ID to map to 0 (user root)"
41 (-1 = current user) will be owned by root in the resulting image.
46 int "Group ID to map to 0 (group root)"
51 (-1 = current group) will be owned by root in the resulting image.
112 prompt "Built-in initramfs compression mode"
118 decompression speed. Compression speed is only relevant
119 when building a kernel. Decompression speed is relevant at
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
[all …]
H A Dtoshiba,visconti-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
16 - $ref: /schemas/pci/snps,dw-pcie.yaml#
20 const: toshiba,visconti-pcie
24 - description: Data Bus Interface (DBI) registers.
25 - description: PCIe configuration space region.
26 - description: Visconti specific additional registers.
[all …]
H A Dti,am65-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
26 reg-names:
[all …]
/linux/arch/powerpc/boot/dts/
H A Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dbamboo.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
33 #address-cells = <1>;
34 #size-cells = <0>;
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
42 i-cache-line-size = <32>;
43 d-cache-line-size = <32>;
[all …]
H A Dsequoia.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dyosemite.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
19 max8952,default-mode:
25 max8952,dvs-mode-microvolt:
35 max8952,en-gpio:
40 max8952,ramp-speed:
45 Voltage ramp speed, values map to:
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c1 // SPDX-License-Identifier: GPL-2.0-only
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
[all …]
/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #include <asm-generic/termbits-common.h>
39 speed_t c_ispeed; /* input speed */
40 speed_t c_ospeed; /* output speed */
50 speed_t c_ispeed; /* input speed */
51 speed_t c_ospeed; /* output speed */
58 #define VKILL 3 /* Kill-line character [ICANON] */
60 #define VTIME 5 /* Time-out value (tenths of a second) [!ICANON] */
64 #define VSTART 8 /* Start (X-ON) character [IXON, IXOFF] */
65 #define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF] */
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x_calendar.c1 // SPDX-License-Identifier: GPL-2.0+
20 /* Each entry in the following struct defines properties for a given speed
24 /* Number of devices that requires this speed. */
27 /* Array of devices that requires this speed. */
30 /* Number of slots required for one device running this speed. */
33 /* Gap between two slots for one device running this speed. */
49 return -EINVAL; in lan969x_dsm_cal_idx_get()
58 return -ENOENT; in lan969x_dsm_cal_idx_get()
61 static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) in lan969x_dsm_cal_get_dev() argument
63 return (speed == 10000 ? DSM_CAL_DEV_10G : in lan969x_dsm_cal_get_dev()
[all …]
/linux/Documentation/arch/m68k/
H A Dbuddha-driver.rst8 ------------------------------------------------------------------------
10 Register map of the Buddha IDE controller and the
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8390-grinn-genio-sbc.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Author: Mateusz Koza <mateusz.koza@grinn-global.com>
7 #include <dt-bindings/gpio/gpio.h>
10 chassis-type = "embedded";
23 stdout-path = "serial0:921600n8";
28 compatible = "linaro,optee-tz";
33 reserved-memory {
34 #address-cells = <2>;
35 #size-cells = <2>;
39 * 12 MiB reserved for OP-TEE (BL32)
[all …]
/linux/net/ethtool/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 [NETIF_F_SG_BIT] = "tx-scatter-gather",
18 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
19 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-i
106 __LINK_MODE_NAME(speed,type,duplex) global() argument
108 __DEFINE_LINK_MODE_NAME(speed,type,duplex) global() argument
1139 struct ethtool_forced_speed_map *map = &maps[i]; ethtool_forced_speed_maps_init() local
[all...]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos2200-g0s.dts1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Samsung Galaxy S22+ (g0s/SM-S906B) device tree source
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "Samsung Galaxy S22+ (SM-S906B)";
17 chassis-type = "handset";
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]

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