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Searched +full:speed +full:- +full:bins (Results 1 – 12 of 12) sorted by relevance

/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996pro.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ opp-table-cluster0;
10 /delete-node/ opp-table-cluster1;
13 * On MSM8996 Pro the cpufreq driver shifts speed bins into the high
14 * nibble of supported hw, so speed bin 0 becomes 0x10, speed bin 1
15 * becomes 0x20, speed 2 becomes 0x40.
18 cluster0_opp: opp-table-cluster0 {
19 compatible = "operating-points-v2-kryo-cpu";
20 nvmem-cells = <&speedbin_efuse>;
21 opp-shared;
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/linux/include/dt-bindings/clock/
H A Drk3399-ddr.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
7 * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
11 /* DDR3-800 (5-5-5) */
13 /* DDR3-800 (6-6-6) */
15 /* DDR3-1066 (6-6-6) */
17 /* DDR3-1066 (7-7-7) */
19 /* DDR3-1066 (8-8-8) */
21 /* DDR3-1333 (7-7-7) */
23 /* DDR3-1333 (8-8-8) */
25 /* DDR3-1333 (9-9-9) */
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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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/linux/arch/arc/boot/dts/
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
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/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
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/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_vf.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
15 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; in qed_vf_pf_prep()
23 mutex_lock(&(p_iov->mutex)); in qed_vf_pf_prep()
31 p_iov->offset = (u8 *)p_iov->vf2pf_request; in qed_vf_pf_prep()
33 /* Clear mailbox - both request and reply */ in qed_vf_pf_prep()
34 memset(p_iov->vf2pf_request, 0, sizeof(union vfpf_tlvs)); in qed_vf_pf_prep()
35 memset(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs)); in qed_vf_pf_prep()
38 p_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, type, length); in qed_vf_pf_prep()
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H A Dqed_vf.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
3 * Copyright (c) 2015-2017 QLogic Corporation
45 /* general tlv header (used for both vf->pf request and pf->vf response) */
51 /* header of first vf->pf tlv carries the offset used to calculate response
60 /* header of pf->vf tlvs, carries the status of handling the request */
88 #define VFPF_ACQUIRE_CAP_PRE_FP_HSI BIT(0) /* VF pre-FP hsi version */
90 /* A requirement for supporting multi-Tx queues on a single queue-zone,
166 * mechanism [version-based] and allow a VF that can't be supported to pass
194 * non-matching versions to shed light in VF about failure.
227 /* Extended queue information - additional index for reference inside qzone.
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H A Dqed_sriov.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
27 return le16_to_cpu(entity_id) - MAX_NUM_PFS; in qed_vf_from_entity_id()
34 if (p_vf->acquire.vfdev_info.eth_fp_hsi_minor == in qed_vf_calculate_legacy()
38 if (!(p_vf->acquire.vfdev_info.capabilities & in qed_vf_calculate_legacy()
51 int rc = -EINVAL; in qed_sp_vf_start()
57 init_data.opaque_fid = p_vf->opaque_fid; in qed_sp_vf_start()
66 p_ramrod = &p_ent->ramrod.vf_start; in qed_sp_vf_start()
68 p_ramrod->vf_id = GET_FIELD(p_vf->concrete_fid, PXP_CONCRETE_FID_VFID); in qed_sp_vf_start()
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/linux/drivers/net/dsa/b53/
H A Db53_common.c4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
230 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
231 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
237 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); in b53_do_vlan_op()
242 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); in b53_do_vlan_op()
249 return -EIO; in b53_do_vlan_op()
258 if (vlan->members) { in b53_set_vlan_entry()
259 entry = ((vlan->untag & VA_UNTAG_MASK_25) << in b53_set_vlan_entry()
260 VA_UNTAG_S_25) | vlan->members; in b53_set_vlan_entry()
261 if (dev->core_rev >= 3) in b53_set_vlan_entry()
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/linux/include/linux/
H A Dmmzone.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/pageblock-flags.h>
20 #include <linux/page-flags-layout.h>
23 #include <linux/page-flags.h>
28 /* Free memory management - zoned buddy allocator. */
99 * __dump_folio() in mm/debug.c passes a folio pointer to on-stack struct folio,
103 (get_pfnblock_migratetype(&folio->page, pfn) == MIGRATE_CMA)
136 get_pageblock_migratetype(&folio->page)
220 NR_KERNEL_MISC_RECLAIMABLE, /* reclaimable non-slab kernel pages */
244 * Not rate-limited (NRL) candidate pages for those can be promoted
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/linux/mm/
H A Dvmscan.c1 // SPDX-License-Identifier: GPL-2.0
31 #include <linux/backing-dev.h>
45 #include <linux/memory-tiers.h>
188 if ((_folio)->lru.prev != _base) { \
191 prev = lru_to_folio(&(_folio->lru)); \
192 prefetchw(&prev->_field); \
209 return sc->target_mem_cgroup; in cgroup_reclaim()
218 return !sc->target_mem_cgroup || mem_cgroup_is_root(sc->target_mem_cgroup); in root_reclaim()
222 * writeback_throttling_sane - is the usual dirty throttling mechanism available?
247 if (sc->proactive && sc->proactive_swappiness) in sc_swappiness()
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