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/linux/Documentation/devicetree/bindings/timer/
H A Darm,sp804.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM sp804 Dual Timers
10 - Haojian Zhuang <haojian.zhuang@linaro.org>
13 The Arm SP804 IP implements two independent timers, configurable for
14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared, but can be gated and prescaled
18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
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/linux/drivers/clocksource/
H A Dtimer-sp804.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/clocksource/timer-sp.c
5 * Copyright (C) 1999 - 2003 ARM Limited
16 #include <linux/irq.h>
24 #include "timer-sp.h"
26 /* Hisilicon 64-bit timer(a variant of ARM SP804) */
67 clk = clk_get_sys("sp804", name); in sp804_get_clock_rate()
102 return ~readl_relaxed(sched_clkevt->value); in sp804_read()
115 return -EINVAL; in sp804_clocksource_and_sched_clock_init()
119 writel(0, clkevt->ctrl); in sp804_clocksource_and_sched_clock_init()
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/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pb11mp.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb11mp";
45 * The PB11MPCore has 512 MiB memory @ 0x70000000
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
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H A Darm-realview-pb1176.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb1176";
50 vmmc: regulator-vmmc {
51 compatible = "regulator-fixed";
52 regulator-name = "vmmc";
53 regulator-min-microvolt = <3300000>;
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
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H A Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
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