Searched +full:socfpga +full:- +full:a10 +full:- +full:ocram +full:- +full:ecc (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/arm/mach-socfpga/ |
| H A D | ocram.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 /* Find the OCRAM EDAC device tree node */ in socfpga_init_ocram_ecc()
21 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); in socfpga_init_ocram_ecc()
23 pr_err("Unable to find socfpga-ocram-ecc\n"); in socfpga_init_ocram_ecc()
30 pr_err("Unable to map OCRAM ecc regs.\n"); in socfpga_init_ocram_ecc()
34 /* Clear any pending OCRAM ECC interrupts, then enable ECC */ in socfpga_init_ocram_ecc()
41 /* Arria10 OCRAM Section */
58 /* ECC Manager Defines */
89 * This function uses the memory initialization block in the Arria10 ECC
90 * controller to initialize/clear the entire memory data and ECC data.
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| /linux/arch/arm64/boot/dts/intel/ |
| H A D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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| /linux/arch/arm64/boot/dts/altera/ |
| H A D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| /linux/drivers/edac/ |
| H A D | altera_edac.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
12 #include <linux/firmware/intel/stratix10-smc.h>
17 #include <linux/mfd/altera-sysmgr.h>
84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; in altr_sdram_mc_err_handler()
85 const struct altr_sdram_prv_data *priv = drvdata->data; in altr_sdram_mc_err_handler()
88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); in altr_sdram_mc_err_handler()
90 if (status & priv->ecc_stat_ue_mask) { in altr_sdram_mc_err_handler()
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