1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/io.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/property.h>
16 #include <linux/pwrseq/consumer.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/remoteproc/qcom_rproc.h>
19 #include <linux/of_reserved_mem.h>
20 #include <linux/iommu.h>
21
22 #include "ce.h"
23 #include "coredump.h"
24 #include "debug.h"
25 #include "hif.h"
26 #include "htc.h"
27 #include "snoc.h"
28
29 #define ATH10K_SNOC_RX_POST_RETRY_MS 50
30 #define CE_POLL_PIPE 4
31 #define ATH10K_SNOC_WAKE_IRQ 2
32
33 static char *const ce_name[] = {
34 "WLAN_CE_0",
35 "WLAN_CE_1",
36 "WLAN_CE_2",
37 "WLAN_CE_3",
38 "WLAN_CE_4",
39 "WLAN_CE_5",
40 "WLAN_CE_6",
41 "WLAN_CE_7",
42 "WLAN_CE_8",
43 "WLAN_CE_9",
44 "WLAN_CE_10",
45 "WLAN_CE_11",
46 };
47
48 static const char * const ath10k_regulators[] = {
49 "vdd-0.8-cx-mx",
50 "vdd-1.8-xo",
51 "vdd-1.3-rfa",
52 "vdd-3.3-ch0",
53 "vdd-3.3-ch1",
54 };
55
56 static const char * const ath10k_clocks[] = {
57 "cxo_ref_clk_pin", "qdss",
58 };
59
60 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
61 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
62 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
63 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
64 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
65 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
66
67 static const struct ath10k_snoc_drv_priv drv_priv = {
68 .hw_rev = ATH10K_HW_WCN3990,
69 .dma_mask = DMA_BIT_MASK(35),
70 .msa_size = 0x100000,
71 };
72
73 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C
74 #define WCN3990_DST_WR_IDX_OFFSET 0x40
75
76 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = {
77 {
78 .ce_id = __cpu_to_le16(0),
79 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
80 },
81
82 {
83 .ce_id = __cpu_to_le16(3),
84 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
85 },
86
87 {
88 .ce_id = __cpu_to_le16(4),
89 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
90 },
91
92 {
93 .ce_id = __cpu_to_le16(5),
94 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
95 },
96
97 {
98 .ce_id = __cpu_to_le16(7),
99 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
100 },
101
102 {
103 .ce_id = __cpu_to_le16(1),
104 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
105 },
106
107 {
108 .ce_id = __cpu_to_le16(2),
109 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
110 },
111
112 {
113 .ce_id = __cpu_to_le16(7),
114 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
115 },
116
117 {
118 .ce_id = __cpu_to_le16(8),
119 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
120 },
121
122 {
123 .ce_id = __cpu_to_le16(9),
124 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
125 },
126
127 {
128 .ce_id = __cpu_to_le16(10),
129 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
130 },
131
132 {
133 .ce_id = __cpu_to_le16(11),
134 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
135 },
136 };
137
138 static struct ce_attr host_ce_config_wlan[] = {
139 /* CE0: host->target HTC control streams */
140 {
141 .flags = CE_ATTR_FLAGS,
142 .src_nentries = 16,
143 .src_sz_max = 2048,
144 .dest_nentries = 0,
145 .send_cb = ath10k_snoc_htc_tx_cb,
146 },
147
148 /* CE1: target->host HTT + HTC control */
149 {
150 .flags = CE_ATTR_FLAGS,
151 .src_nentries = 0,
152 .src_sz_max = 2048,
153 .dest_nentries = 512,
154 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
155 },
156
157 /* CE2: target->host WMI */
158 {
159 .flags = CE_ATTR_FLAGS,
160 .src_nentries = 0,
161 .src_sz_max = 2048,
162 .dest_nentries = 64,
163 .recv_cb = ath10k_snoc_htc_rx_cb,
164 },
165
166 /* CE3: host->target WMI */
167 {
168 .flags = CE_ATTR_FLAGS,
169 .src_nentries = 32,
170 .src_sz_max = 2048,
171 .dest_nentries = 0,
172 .send_cb = ath10k_snoc_htc_tx_cb,
173 },
174
175 /* CE4: host->target HTT */
176 {
177 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
178 .src_nentries = 2048,
179 .src_sz_max = 256,
180 .dest_nentries = 0,
181 .send_cb = ath10k_snoc_htt_tx_cb,
182 },
183
184 /* CE5: target->host HTT (ipa_uc->target ) */
185 {
186 .flags = CE_ATTR_FLAGS,
187 .src_nentries = 0,
188 .src_sz_max = 512,
189 .dest_nentries = 512,
190 .recv_cb = ath10k_snoc_htt_rx_cb,
191 },
192
193 /* CE6: target autonomous hif_memcpy */
194 {
195 .flags = CE_ATTR_FLAGS,
196 .src_nentries = 0,
197 .src_sz_max = 0,
198 .dest_nentries = 0,
199 },
200
201 /* CE7: ce_diag, the Diagnostic Window */
202 {
203 .flags = CE_ATTR_FLAGS,
204 .src_nentries = 2,
205 .src_sz_max = 2048,
206 .dest_nentries = 2,
207 },
208
209 /* CE8: Target to uMC */
210 {
211 .flags = CE_ATTR_FLAGS,
212 .src_nentries = 0,
213 .src_sz_max = 2048,
214 .dest_nentries = 128,
215 },
216
217 /* CE9 target->host HTT */
218 {
219 .flags = CE_ATTR_FLAGS,
220 .src_nentries = 0,
221 .src_sz_max = 2048,
222 .dest_nentries = 512,
223 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
224 },
225
226 /* CE10: target->host HTT */
227 {
228 .flags = CE_ATTR_FLAGS,
229 .src_nentries = 0,
230 .src_sz_max = 2048,
231 .dest_nentries = 512,
232 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
233 },
234
235 /* CE11: target -> host PKTLOG */
236 {
237 .flags = CE_ATTR_FLAGS,
238 .src_nentries = 0,
239 .src_sz_max = 2048,
240 .dest_nentries = 512,
241 .recv_cb = ath10k_snoc_pktlog_rx_cb,
242 },
243 };
244
245 static struct ce_pipe_config target_ce_config_wlan[] = {
246 /* CE0: host->target HTC control and raw streams */
247 {
248 .pipenum = __cpu_to_le32(0),
249 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
250 .nentries = __cpu_to_le32(32),
251 .nbytes_max = __cpu_to_le32(2048),
252 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
253 .reserved = __cpu_to_le32(0),
254 },
255
256 /* CE1: target->host HTT + HTC control */
257 {
258 .pipenum = __cpu_to_le32(1),
259 .pipedir = __cpu_to_le32(PIPEDIR_IN),
260 .nentries = __cpu_to_le32(32),
261 .nbytes_max = __cpu_to_le32(2048),
262 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
263 .reserved = __cpu_to_le32(0),
264 },
265
266 /* CE2: target->host WMI */
267 {
268 .pipenum = __cpu_to_le32(2),
269 .pipedir = __cpu_to_le32(PIPEDIR_IN),
270 .nentries = __cpu_to_le32(64),
271 .nbytes_max = __cpu_to_le32(2048),
272 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
273 .reserved = __cpu_to_le32(0),
274 },
275
276 /* CE3: host->target WMI */
277 {
278 .pipenum = __cpu_to_le32(3),
279 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
280 .nentries = __cpu_to_le32(32),
281 .nbytes_max = __cpu_to_le32(2048),
282 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
283 .reserved = __cpu_to_le32(0),
284 },
285
286 /* CE4: host->target HTT */
287 {
288 .pipenum = __cpu_to_le32(4),
289 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
290 .nentries = __cpu_to_le32(256),
291 .nbytes_max = __cpu_to_le32(256),
292 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
293 .reserved = __cpu_to_le32(0),
294 },
295
296 /* CE5: target->host HTT (HIF->HTT) */
297 {
298 .pipenum = __cpu_to_le32(5),
299 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
300 .nentries = __cpu_to_le32(1024),
301 .nbytes_max = __cpu_to_le32(64),
302 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
303 .reserved = __cpu_to_le32(0),
304 },
305
306 /* CE6: Reserved for target autonomous hif_memcpy */
307 {
308 .pipenum = __cpu_to_le32(6),
309 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
310 .nentries = __cpu_to_le32(32),
311 .nbytes_max = __cpu_to_le32(16384),
312 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
313 .reserved = __cpu_to_le32(0),
314 },
315
316 /* CE7 used only by Host */
317 {
318 .pipenum = __cpu_to_le32(7),
319 .pipedir = __cpu_to_le32(4),
320 .nentries = __cpu_to_le32(0),
321 .nbytes_max = __cpu_to_le32(0),
322 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
323 .reserved = __cpu_to_le32(0),
324 },
325
326 /* CE8 Target to uMC */
327 {
328 .pipenum = __cpu_to_le32(8),
329 .pipedir = __cpu_to_le32(PIPEDIR_IN),
330 .nentries = __cpu_to_le32(32),
331 .nbytes_max = __cpu_to_le32(2048),
332 .flags = __cpu_to_le32(0),
333 .reserved = __cpu_to_le32(0),
334 },
335
336 /* CE9 target->host HTT */
337 {
338 .pipenum = __cpu_to_le32(9),
339 .pipedir = __cpu_to_le32(PIPEDIR_IN),
340 .nentries = __cpu_to_le32(32),
341 .nbytes_max = __cpu_to_le32(2048),
342 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
343 .reserved = __cpu_to_le32(0),
344 },
345
346 /* CE10 target->host HTT */
347 {
348 .pipenum = __cpu_to_le32(10),
349 .pipedir = __cpu_to_le32(PIPEDIR_IN),
350 .nentries = __cpu_to_le32(32),
351 .nbytes_max = __cpu_to_le32(2048),
352 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
353 .reserved = __cpu_to_le32(0),
354 },
355
356 /* CE11 target autonomous qcache memcpy */
357 {
358 .pipenum = __cpu_to_le32(11),
359 .pipedir = __cpu_to_le32(PIPEDIR_IN),
360 .nentries = __cpu_to_le32(32),
361 .nbytes_max = __cpu_to_le32(2048),
362 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
363 .reserved = __cpu_to_le32(0),
364 },
365 };
366
367 static struct ce_service_to_pipe target_service_to_ce_map_wlan[] = {
368 {
369 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
370 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
371 __cpu_to_le32(3),
372 },
373 {
374 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
375 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
376 __cpu_to_le32(2),
377 },
378 {
379 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
380 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
381 __cpu_to_le32(3),
382 },
383 {
384 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
385 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
386 __cpu_to_le32(2),
387 },
388 {
389 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
390 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
391 __cpu_to_le32(3),
392 },
393 {
394 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
395 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
396 __cpu_to_le32(2),
397 },
398 {
399 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
400 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
401 __cpu_to_le32(3),
402 },
403 {
404 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
405 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
406 __cpu_to_le32(2),
407 },
408 {
409 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
410 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
411 __cpu_to_le32(3),
412 },
413 {
414 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
415 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
416 __cpu_to_le32(2),
417 },
418 {
419 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
420 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
421 __cpu_to_le32(0),
422 },
423 {
424 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
425 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
426 __cpu_to_le32(2),
427 },
428 { /* not used */
429 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
430 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
431 __cpu_to_le32(0),
432 },
433 { /* not used */
434 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
435 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
436 __cpu_to_le32(2),
437 },
438 {
439 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
440 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
441 __cpu_to_le32(4),
442 },
443 {
444 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
445 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
446 __cpu_to_le32(1),
447 },
448 { /* not used */
449 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
450 __cpu_to_le32(PIPEDIR_OUT),
451 __cpu_to_le32(5),
452 },
453 { /* in = DL = target -> host */
454 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG),
455 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
456 __cpu_to_le32(9),
457 },
458 { /* in = DL = target -> host */
459 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG),
460 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
461 __cpu_to_le32(10),
462 },
463 { /* in = DL = target -> host pktlog */
464 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG),
465 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
466 __cpu_to_le32(11),
467 },
468 /* (Additions here) */
469
470 { /* must be last */
471 __cpu_to_le32(0),
472 __cpu_to_le32(0),
473 __cpu_to_le32(0),
474 },
475 };
476
ath10k_snoc_write32(struct ath10k * ar,u32 offset,u32 value)477 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value)
478 {
479 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
480
481 iowrite32(value, ar_snoc->mem + offset);
482 }
483
ath10k_snoc_read32(struct ath10k * ar,u32 offset)484 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset)
485 {
486 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
487 u32 val;
488
489 val = ioread32(ar_snoc->mem + offset);
490
491 return val;
492 }
493
__ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe * pipe)494 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe)
495 {
496 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
497 struct ath10k *ar = pipe->hif_ce_state;
498 struct ath10k_ce *ce = ath10k_ce_priv(ar);
499 struct sk_buff *skb;
500 dma_addr_t paddr;
501 int ret;
502
503 skb = dev_alloc_skb(pipe->buf_sz);
504 if (!skb)
505 return -ENOMEM;
506
507 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
508
509 paddr = dma_map_single(ar->dev, skb->data,
510 skb->len + skb_tailroom(skb),
511 DMA_FROM_DEVICE);
512 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
513 ath10k_warn(ar, "failed to dma map snoc rx buf\n");
514 dev_kfree_skb_any(skb);
515 return -EIO;
516 }
517
518 ATH10K_SKB_RXCB(skb)->paddr = paddr;
519
520 spin_lock_bh(&ce->ce_lock);
521 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
522 spin_unlock_bh(&ce->ce_lock);
523 if (ret) {
524 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
525 DMA_FROM_DEVICE);
526 dev_kfree_skb_any(skb);
527 return ret;
528 }
529
530 return 0;
531 }
532
ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe * pipe)533 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe)
534 {
535 struct ath10k *ar = pipe->hif_ce_state;
536 struct ath10k_ce *ce = ath10k_ce_priv(ar);
537 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
538 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
539 int ret, num;
540
541 if (pipe->buf_sz == 0)
542 return;
543
544 if (!ce_pipe->dest_ring)
545 return;
546
547 spin_lock_bh(&ce->ce_lock);
548 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
549 spin_unlock_bh(&ce->ce_lock);
550 while (num--) {
551 ret = __ath10k_snoc_rx_post_buf(pipe);
552 if (ret) {
553 if (ret == -ENOSPC)
554 break;
555 ath10k_warn(ar, "failed to post rx buf: %d\n", ret);
556 mod_timer(&ar_snoc->rx_post_retry, jiffies +
557 ATH10K_SNOC_RX_POST_RETRY_MS);
558 break;
559 }
560 }
561 }
562
ath10k_snoc_rx_post(struct ath10k * ar)563 static void ath10k_snoc_rx_post(struct ath10k *ar)
564 {
565 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
566 int i;
567
568 for (i = 0; i < CE_COUNT; i++)
569 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]);
570 }
571
ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe * ce_state,void (* callback)(struct ath10k * ar,struct sk_buff * skb))572 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state,
573 void (*callback)(struct ath10k *ar,
574 struct sk_buff *skb))
575 {
576 struct ath10k *ar = ce_state->ar;
577 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
578 struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id];
579 struct sk_buff *skb;
580 struct sk_buff_head list;
581 void *transfer_context;
582 unsigned int nbytes, max_nbytes;
583
584 __skb_queue_head_init(&list);
585 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
586 &nbytes) == 0) {
587 skb = transfer_context;
588 max_nbytes = skb->len + skb_tailroom(skb);
589 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
590 max_nbytes, DMA_FROM_DEVICE);
591
592 if (unlikely(max_nbytes < nbytes)) {
593 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)\n",
594 nbytes, max_nbytes);
595 dev_kfree_skb_any(skb);
596 continue;
597 }
598
599 skb_put(skb, nbytes);
600 __skb_queue_tail(&list, skb);
601 }
602
603 while ((skb = __skb_dequeue(&list))) {
604 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n",
605 ce_state->id, skb->len);
606
607 callback(ar, skb);
608 }
609
610 ath10k_snoc_rx_post_pipe(pipe_info);
611 }
612
ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe * ce_state)613 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
614 {
615 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
616 }
617
ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe * ce_state)618 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
619 {
620 /* CE4 polling needs to be done whenever CE pipe which transports
621 * HTT Rx (target->host) is processed.
622 */
623 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
624
625 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
626 }
627
628 /* Called by lower (CE) layer when data is received from the Target.
629 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data.
630 */
ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe * ce_state)631 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
632 {
633 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
634 }
635
ath10k_snoc_htt_rx_deliver(struct ath10k * ar,struct sk_buff * skb)636 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
637 {
638 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
639 ath10k_htt_t2h_msg_handler(ar, skb);
640 }
641
ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe * ce_state)642 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
643 {
644 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
645 ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver);
646 }
647
ath10k_snoc_rx_replenish_retry(struct timer_list * t)648 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
649 {
650 struct ath10k_snoc *ar_snoc = timer_container_of(ar_snoc, t,
651 rx_post_retry);
652 struct ath10k *ar = ar_snoc->ar;
653
654 ath10k_snoc_rx_post(ar);
655 }
656
ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe * ce_state)657 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
658 {
659 struct ath10k *ar = ce_state->ar;
660 struct sk_buff_head list;
661 struct sk_buff *skb;
662
663 __skb_queue_head_init(&list);
664 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
665 if (!skb)
666 continue;
667
668 __skb_queue_tail(&list, skb);
669 }
670
671 while ((skb = __skb_dequeue(&list)))
672 ath10k_htc_tx_completion_handler(ar, skb);
673 }
674
ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe * ce_state)675 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
676 {
677 struct ath10k *ar = ce_state->ar;
678 struct sk_buff *skb;
679
680 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
681 if (!skb)
682 continue;
683
684 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
685 skb->len, DMA_TO_DEVICE);
686 ath10k_htt_hif_tx_complete(ar, skb);
687 }
688 }
689
ath10k_snoc_hif_tx_sg(struct ath10k * ar,u8 pipe_id,struct ath10k_hif_sg_item * items,int n_items)690 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
691 struct ath10k_hif_sg_item *items, int n_items)
692 {
693 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
694 struct ath10k_ce *ce = ath10k_ce_priv(ar);
695 struct ath10k_snoc_pipe *snoc_pipe;
696 struct ath10k_ce_pipe *ce_pipe;
697 int err, i = 0;
698
699 snoc_pipe = &ar_snoc->pipe_info[pipe_id];
700 ce_pipe = snoc_pipe->ce_hdl;
701 spin_lock_bh(&ce->ce_lock);
702
703 for (i = 0; i < n_items - 1; i++) {
704 ath10k_dbg(ar, ATH10K_DBG_SNOC,
705 "snoc tx item %d paddr %pad len %d n_items %d\n",
706 i, &items[i].paddr, items[i].len, n_items);
707
708 err = ath10k_ce_send_nolock(ce_pipe,
709 items[i].transfer_context,
710 items[i].paddr,
711 items[i].len,
712 items[i].transfer_id,
713 CE_SEND_FLAG_GATHER);
714 if (err)
715 goto err;
716 }
717
718 ath10k_dbg(ar, ATH10K_DBG_SNOC,
719 "snoc tx item %d paddr %pad len %d n_items %d\n",
720 i, &items[i].paddr, items[i].len, n_items);
721
722 err = ath10k_ce_send_nolock(ce_pipe,
723 items[i].transfer_context,
724 items[i].paddr,
725 items[i].len,
726 items[i].transfer_id,
727 0);
728 if (err)
729 goto err;
730
731 spin_unlock_bh(&ce->ce_lock);
732
733 return 0;
734
735 err:
736 for (; i > 0; i--)
737 __ath10k_ce_send_revert(ce_pipe);
738
739 spin_unlock_bh(&ce->ce_lock);
740 return err;
741 }
742
ath10k_snoc_hif_get_target_info(struct ath10k * ar,struct bmi_target_info * target_info)743 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar,
744 struct bmi_target_info *target_info)
745 {
746 target_info->version = ATH10K_HW_WCN3990;
747 target_info->type = ATH10K_HW_WCN3990;
748
749 return 0;
750 }
751
ath10k_snoc_hif_get_free_queue_number(struct ath10k * ar,u8 pipe)752 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
753 {
754 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
755
756 ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n");
757
758 return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl);
759 }
760
ath10k_snoc_hif_send_complete_check(struct ath10k * ar,u8 pipe,int force)761 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe,
762 int force)
763 {
764 int resources;
765
766 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n");
767
768 if (!force) {
769 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe);
770
771 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
772 return;
773 }
774 ath10k_ce_per_engine_service(ar, pipe);
775 }
776
ath10k_snoc_hif_map_service_to_pipe(struct ath10k * ar,u16 service_id,u8 * ul_pipe,u8 * dl_pipe)777 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar,
778 u16 service_id,
779 u8 *ul_pipe, u8 *dl_pipe)
780 {
781 const struct ce_service_to_pipe *entry;
782 bool ul_set = false, dl_set = false;
783 int i;
784
785 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n");
786
787 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
788 entry = &target_service_to_ce_map_wlan[i];
789
790 if (__le32_to_cpu(entry->service_id) != service_id)
791 continue;
792
793 switch (__le32_to_cpu(entry->pipedir)) {
794 case PIPEDIR_NONE:
795 break;
796 case PIPEDIR_IN:
797 WARN_ON(dl_set);
798 *dl_pipe = __le32_to_cpu(entry->pipenum);
799 dl_set = true;
800 break;
801 case PIPEDIR_OUT:
802 WARN_ON(ul_set);
803 *ul_pipe = __le32_to_cpu(entry->pipenum);
804 ul_set = true;
805 break;
806 case PIPEDIR_INOUT:
807 WARN_ON(dl_set);
808 WARN_ON(ul_set);
809 *dl_pipe = __le32_to_cpu(entry->pipenum);
810 *ul_pipe = __le32_to_cpu(entry->pipenum);
811 dl_set = true;
812 ul_set = true;
813 break;
814 }
815 }
816
817 if (!ul_set || !dl_set)
818 return -ENOENT;
819
820 return 0;
821 }
822
ath10k_snoc_hif_get_default_pipe(struct ath10k * ar,u8 * ul_pipe,u8 * dl_pipe)823 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar,
824 u8 *ul_pipe, u8 *dl_pipe)
825 {
826 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n");
827
828 (void)ath10k_snoc_hif_map_service_to_pipe(ar,
829 ATH10K_HTC_SVC_ID_RSVD_CTRL,
830 ul_pipe, dl_pipe);
831 }
832
ath10k_snoc_irq_disable(struct ath10k * ar)833 static inline void ath10k_snoc_irq_disable(struct ath10k *ar)
834 {
835 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
836 int id;
837
838 for (id = 0; id < CE_COUNT_MAX; id++)
839 disable_irq(ar_snoc->ce_irqs[id].irq_line);
840 }
841
ath10k_snoc_irq_enable(struct ath10k * ar)842 static inline void ath10k_snoc_irq_enable(struct ath10k *ar)
843 {
844 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
845 int id;
846
847 for (id = 0; id < CE_COUNT_MAX; id++)
848 enable_irq(ar_snoc->ce_irqs[id].irq_line);
849 }
850
ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe * snoc_pipe)851 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
852 {
853 struct ath10k_ce_pipe *ce_pipe;
854 struct ath10k_ce_ring *ce_ring;
855 struct sk_buff *skb;
856 struct ath10k *ar;
857 int i;
858
859 ar = snoc_pipe->hif_ce_state;
860 ce_pipe = snoc_pipe->ce_hdl;
861 ce_ring = ce_pipe->dest_ring;
862
863 if (!ce_ring)
864 return;
865
866 if (!snoc_pipe->buf_sz)
867 return;
868
869 for (i = 0; i < ce_ring->nentries; i++) {
870 skb = ce_ring->per_transfer_context[i];
871 if (!skb)
872 continue;
873
874 ce_ring->per_transfer_context[i] = NULL;
875
876 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
877 skb->len + skb_tailroom(skb),
878 DMA_FROM_DEVICE);
879 dev_kfree_skb_any(skb);
880 }
881 }
882
ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe * snoc_pipe)883 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
884 {
885 struct ath10k_ce_pipe *ce_pipe;
886 struct ath10k_ce_ring *ce_ring;
887 struct sk_buff *skb;
888 struct ath10k *ar;
889 int i;
890
891 ar = snoc_pipe->hif_ce_state;
892 ce_pipe = snoc_pipe->ce_hdl;
893 ce_ring = ce_pipe->src_ring;
894
895 if (!ce_ring)
896 return;
897
898 if (!snoc_pipe->buf_sz)
899 return;
900
901 for (i = 0; i < ce_ring->nentries; i++) {
902 skb = ce_ring->per_transfer_context[i];
903 if (!skb)
904 continue;
905
906 ce_ring->per_transfer_context[i] = NULL;
907
908 ath10k_htc_tx_completion_handler(ar, skb);
909 }
910 }
911
ath10k_snoc_buffer_cleanup(struct ath10k * ar)912 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar)
913 {
914 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
915 struct ath10k_snoc_pipe *pipe_info;
916 int pipe_num;
917
918 timer_delete_sync(&ar_snoc->rx_post_retry);
919 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
920 pipe_info = &ar_snoc->pipe_info[pipe_num];
921 ath10k_snoc_rx_pipe_cleanup(pipe_info);
922 ath10k_snoc_tx_pipe_cleanup(pipe_info);
923 }
924 }
925
ath10k_snoc_hif_stop(struct ath10k * ar)926 static void ath10k_snoc_hif_stop(struct ath10k *ar)
927 {
928 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags))
929 ath10k_snoc_irq_disable(ar);
930
931 ath10k_core_napi_sync_disable(ar);
932 ath10k_snoc_buffer_cleanup(ar);
933 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
934 }
935
ath10k_snoc_hif_start(struct ath10k * ar)936 static int ath10k_snoc_hif_start(struct ath10k *ar)
937 {
938 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
939
940 bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX);
941
942 netif_threaded_enable(ar->napi_dev);
943 ath10k_core_napi_enable(ar);
944 /* IRQs are left enabled when we restart due to a firmware crash */
945 if (!test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
946 ath10k_snoc_irq_enable(ar);
947 ath10k_snoc_rx_post(ar);
948
949 clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
950
951 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
952
953 return 0;
954 }
955
ath10k_snoc_init_pipes(struct ath10k * ar)956 static int ath10k_snoc_init_pipes(struct ath10k *ar)
957 {
958 int i, ret;
959
960 for (i = 0; i < CE_COUNT; i++) {
961 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
962 if (ret) {
963 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
964 i, ret);
965 return ret;
966 }
967 }
968
969 return 0;
970 }
971
ath10k_snoc_wlan_enable(struct ath10k * ar,enum ath10k_firmware_mode fw_mode)972 static int ath10k_snoc_wlan_enable(struct ath10k *ar,
973 enum ath10k_firmware_mode fw_mode)
974 {
975 struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX];
976 struct ath10k_qmi_wlan_enable_cfg cfg;
977 enum wlfw_driver_mode_enum_v01 mode;
978 int pipe_num;
979
980 for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) {
981 tgt_cfg[pipe_num].pipe_num =
982 target_ce_config_wlan[pipe_num].pipenum;
983 tgt_cfg[pipe_num].pipe_dir =
984 target_ce_config_wlan[pipe_num].pipedir;
985 tgt_cfg[pipe_num].nentries =
986 target_ce_config_wlan[pipe_num].nentries;
987 tgt_cfg[pipe_num].nbytes_max =
988 target_ce_config_wlan[pipe_num].nbytes_max;
989 tgt_cfg[pipe_num].flags =
990 target_ce_config_wlan[pipe_num].flags;
991 tgt_cfg[pipe_num].reserved = 0;
992 }
993
994 cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) /
995 sizeof(struct ath10k_tgt_pipe_cfg);
996 cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *)
997 &tgt_cfg;
998 cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) /
999 sizeof(struct ath10k_svc_pipe_cfg);
1000 cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *)
1001 &target_service_to_ce_map_wlan;
1002 cfg.num_shadow_reg_cfg = ARRAY_SIZE(target_shadow_reg_cfg_map);
1003 cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *)
1004 &target_shadow_reg_cfg_map;
1005
1006 switch (fw_mode) {
1007 case ATH10K_FIRMWARE_MODE_NORMAL:
1008 mode = QMI_WLFW_MISSION_V01;
1009 break;
1010 case ATH10K_FIRMWARE_MODE_UTF:
1011 mode = QMI_WLFW_FTM_V01;
1012 break;
1013 default:
1014 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode);
1015 return -EINVAL;
1016 }
1017
1018 return ath10k_qmi_wlan_enable(ar, &cfg, mode,
1019 NULL);
1020 }
1021
ath10k_hw_power_on(struct ath10k * ar)1022 static int ath10k_hw_power_on(struct ath10k *ar)
1023 {
1024 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1025 int ret;
1026
1027 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n");
1028
1029 ret = pwrseq_enable(ar_snoc->pwrseq);
1030 if (ret)
1031 return ret;
1032
1033 ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs);
1034 if (ret)
1035 goto pwrseq_off;
1036
1037 ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks);
1038 if (ret)
1039 goto vreg_off;
1040
1041 return ret;
1042
1043 vreg_off:
1044 regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1045 pwrseq_off:
1046 pwrseq_disable(ar_snoc->pwrseq);
1047
1048 return ret;
1049 }
1050
ath10k_hw_power_off(struct ath10k * ar)1051 static int ath10k_hw_power_off(struct ath10k *ar)
1052 {
1053 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1054 int ret_seq = 0;
1055 int ret_vreg;
1056
1057 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n");
1058
1059 clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks);
1060
1061 ret_vreg = regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1062
1063 if (ar_snoc->pwrseq)
1064 ret_seq = pwrseq_disable(ar_snoc->pwrseq);
1065
1066 return ret_vreg ? : ret_seq;
1067 }
1068
ath10k_snoc_wlan_disable(struct ath10k * ar)1069 static void ath10k_snoc_wlan_disable(struct ath10k *ar)
1070 {
1071 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1072
1073 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY
1074 * flags are not set, it means that the driver has restarted
1075 * due to a crash inject via debugfs. In this case, the driver
1076 * needs to restart the firmware and hence send qmi wlan disable,
1077 * during the driver restart sequence.
1078 */
1079 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) ||
1080 !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1081 ath10k_qmi_wlan_disable(ar);
1082 }
1083
ath10k_snoc_hif_power_down(struct ath10k * ar)1084 static void ath10k_snoc_hif_power_down(struct ath10k *ar)
1085 {
1086 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
1087
1088 ath10k_snoc_wlan_disable(ar);
1089 ath10k_ce_free_rri(ar);
1090 ath10k_hw_power_off(ar);
1091 }
1092
ath10k_snoc_hif_power_up(struct ath10k * ar,enum ath10k_firmware_mode fw_mode)1093 static int ath10k_snoc_hif_power_up(struct ath10k *ar,
1094 enum ath10k_firmware_mode fw_mode)
1095 {
1096 int ret;
1097
1098 ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n",
1099 __func__, ar->state);
1100
1101 ret = ath10k_hw_power_on(ar);
1102 if (ret) {
1103 ath10k_err(ar, "failed to power on device: %d\n", ret);
1104 return ret;
1105 }
1106
1107 ret = ath10k_snoc_wlan_enable(ar, fw_mode);
1108 if (ret) {
1109 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret);
1110 goto err_hw_power_off;
1111 }
1112
1113 ath10k_ce_alloc_rri(ar);
1114
1115 ret = ath10k_snoc_init_pipes(ar);
1116 if (ret) {
1117 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1118 goto err_free_rri;
1119 }
1120
1121 ath10k_ce_enable_interrupts(ar);
1122
1123 return 0;
1124
1125 err_free_rri:
1126 ath10k_ce_free_rri(ar);
1127 ath10k_snoc_wlan_disable(ar);
1128
1129 err_hw_power_off:
1130 ath10k_hw_power_off(ar);
1131
1132 return ret;
1133 }
1134
ath10k_snoc_hif_set_target_log_mode(struct ath10k * ar,u8 fw_log_mode)1135 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar,
1136 u8 fw_log_mode)
1137 {
1138 u8 fw_dbg_mode;
1139
1140 if (fw_log_mode)
1141 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE;
1142 else
1143 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG;
1144
1145 return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode);
1146 }
1147
1148 #ifdef CONFIG_PM
ath10k_snoc_hif_suspend(struct ath10k * ar)1149 static int ath10k_snoc_hif_suspend(struct ath10k *ar)
1150 {
1151 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1152 int ret;
1153
1154 if (!device_may_wakeup(ar->dev))
1155 return -EPERM;
1156
1157 ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1158 if (ret) {
1159 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret);
1160 return ret;
1161 }
1162
1163 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n");
1164
1165 return ret;
1166 }
1167
ath10k_snoc_hif_resume(struct ath10k * ar)1168 static int ath10k_snoc_hif_resume(struct ath10k *ar)
1169 {
1170 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1171 int ret;
1172
1173 if (!device_may_wakeup(ar->dev))
1174 return -EPERM;
1175
1176 ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1177 if (ret) {
1178 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret);
1179 return ret;
1180 }
1181
1182 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n");
1183
1184 return ret;
1185 }
1186 #endif
1187
1188 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = {
1189 .read32 = ath10k_snoc_read32,
1190 .write32 = ath10k_snoc_write32,
1191 .start = ath10k_snoc_hif_start,
1192 .stop = ath10k_snoc_hif_stop,
1193 .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe,
1194 .get_default_pipe = ath10k_snoc_hif_get_default_pipe,
1195 .power_up = ath10k_snoc_hif_power_up,
1196 .power_down = ath10k_snoc_hif_power_down,
1197 .tx_sg = ath10k_snoc_hif_tx_sg,
1198 .send_complete_check = ath10k_snoc_hif_send_complete_check,
1199 .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number,
1200 .get_target_info = ath10k_snoc_hif_get_target_info,
1201 .set_target_log_mode = ath10k_snoc_hif_set_target_log_mode,
1202
1203 #ifdef CONFIG_PM
1204 .suspend = ath10k_snoc_hif_suspend,
1205 .resume = ath10k_snoc_hif_resume,
1206 #endif
1207 };
1208
1209 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = {
1210 .read32 = ath10k_snoc_read32,
1211 .write32 = ath10k_snoc_write32,
1212 };
1213
ath10k_snoc_get_ce_id_from_irq(struct ath10k * ar,int irq)1214 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
1215 {
1216 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1217 int i;
1218
1219 for (i = 0; i < CE_COUNT_MAX; i++) {
1220 if (ar_snoc->ce_irqs[i].irq_line == irq)
1221 return i;
1222 }
1223 ath10k_err(ar, "No matching CE id for irq %d\n", irq);
1224
1225 return -EINVAL;
1226 }
1227
ath10k_snoc_per_engine_handler(int irq,void * arg)1228 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg)
1229 {
1230 struct ath10k *ar = arg;
1231 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1232 int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq);
1233
1234 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) {
1235 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
1236 ce_id);
1237 return IRQ_HANDLED;
1238 }
1239
1240 ath10k_ce_disable_interrupt(ar, ce_id);
1241 set_bit(ce_id, ar_snoc->pending_ce_irqs);
1242
1243 napi_schedule(&ar->napi);
1244
1245 return IRQ_HANDLED;
1246 }
1247
ath10k_snoc_napi_poll(struct napi_struct * ctx,int budget)1248 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget)
1249 {
1250 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
1251 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1252 int done = 0;
1253 int ce_id;
1254
1255 if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) {
1256 napi_complete(ctx);
1257 return done;
1258 }
1259
1260 for (ce_id = 0; ce_id < CE_COUNT; ce_id++)
1261 if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) {
1262 ath10k_ce_per_engine_service(ar, ce_id);
1263 ath10k_ce_enable_interrupt(ar, ce_id);
1264 }
1265
1266 done = ath10k_htt_txrx_compl_task(ar, budget);
1267
1268 if (done < budget)
1269 napi_complete(ctx);
1270
1271 return done;
1272 }
1273
ath10k_snoc_init_napi(struct ath10k * ar)1274 static void ath10k_snoc_init_napi(struct ath10k *ar)
1275 {
1276 netif_napi_add(ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll);
1277 }
1278
ath10k_snoc_request_irq(struct ath10k * ar)1279 static int ath10k_snoc_request_irq(struct ath10k *ar)
1280 {
1281 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1282 int ret, id;
1283
1284 for (id = 0; id < CE_COUNT_MAX; id++) {
1285 ret = request_irq(ar_snoc->ce_irqs[id].irq_line,
1286 ath10k_snoc_per_engine_handler,
1287 IRQF_NO_AUTOEN, ce_name[id], ar);
1288 if (ret) {
1289 ath10k_err(ar,
1290 "failed to register IRQ handler for CE %d: %d\n",
1291 id, ret);
1292 goto err_irq;
1293 }
1294 }
1295
1296 return 0;
1297
1298 err_irq:
1299 for (id -= 1; id >= 0; id--)
1300 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1301
1302 return ret;
1303 }
1304
ath10k_snoc_free_irq(struct ath10k * ar)1305 static void ath10k_snoc_free_irq(struct ath10k *ar)
1306 {
1307 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1308 int id;
1309
1310 for (id = 0; id < CE_COUNT_MAX; id++)
1311 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1312 }
1313
ath10k_snoc_resource_init(struct ath10k * ar)1314 static int ath10k_snoc_resource_init(struct ath10k *ar)
1315 {
1316 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1317 struct platform_device *pdev;
1318 struct resource *res;
1319 int i, ret = 0;
1320
1321 pdev = ar_snoc->dev;
1322 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
1323 if (!res) {
1324 ath10k_err(ar, "Memory base not found in DT\n");
1325 return -EINVAL;
1326 }
1327
1328 ar_snoc->mem_pa = res->start;
1329 ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa,
1330 resource_size(res));
1331 if (!ar_snoc->mem) {
1332 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n",
1333 &ar_snoc->mem_pa);
1334 return -EINVAL;
1335 }
1336
1337 for (i = 0; i < CE_COUNT; i++) {
1338 ret = platform_get_irq(ar_snoc->dev, i);
1339 if (ret < 0)
1340 return ret;
1341 ar_snoc->ce_irqs[i].irq_line = ret;
1342 }
1343
1344 ret = device_property_read_u32(&pdev->dev, "qcom,xo-cal-data",
1345 &ar_snoc->xo_cal_data);
1346 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc xo-cal-data return %d\n", ret);
1347 if (ret == 0) {
1348 ar_snoc->xo_cal_supported = true;
1349 ath10k_dbg(ar, ATH10K_DBG_SNOC, "xo cal data %x\n",
1350 ar_snoc->xo_cal_data);
1351 }
1352
1353 return 0;
1354 }
1355
ath10k_snoc_quirks_init(struct ath10k * ar)1356 static void ath10k_snoc_quirks_init(struct ath10k *ar)
1357 {
1358 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1359 struct device *dev = &ar_snoc->dev->dev;
1360
1361 /* ignore errors, keep NULL if there is no property */
1362 of_property_read_string(dev->of_node, "firmware-name", &ar->board_name);
1363
1364 if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-8bit-quirk"))
1365 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags);
1366
1367 if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-skip-quirk"))
1368 set_bit(ATH10K_SNOC_FLAG_SKIP_HOST_CAP_QUIRK, &ar_snoc->flags);
1369 }
1370
ath10k_snoc_fw_indication(struct ath10k * ar,u64 type)1371 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type)
1372 {
1373 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1374 struct ath10k_bus_params bus_params = {};
1375 int ret;
1376
1377 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags))
1378 return 0;
1379
1380 switch (type) {
1381 case ATH10K_QMI_EVENT_FW_READY_IND:
1382 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) {
1383 ath10k_core_start_recovery(ar);
1384 break;
1385 }
1386
1387 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
1388 bus_params.chip_id = ar_snoc->target_info.soc_version;
1389 ret = ath10k_core_register(ar, &bus_params);
1390 if (ret) {
1391 ath10k_err(ar, "Failed to register driver core: %d\n",
1392 ret);
1393 return ret;
1394 }
1395 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags);
1396 break;
1397 case ATH10K_QMI_EVENT_FW_DOWN_IND:
1398 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1399 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1400 break;
1401 default:
1402 ath10k_err(ar, "invalid fw indication: %llx\n", type);
1403 return -EINVAL;
1404 }
1405
1406 return 0;
1407 }
1408
ath10k_snoc_setup_resource(struct ath10k * ar)1409 static int ath10k_snoc_setup_resource(struct ath10k *ar)
1410 {
1411 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1412 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1413 struct ath10k_snoc_pipe *pipe;
1414 int i, ret;
1415
1416 timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0);
1417 spin_lock_init(&ce->ce_lock);
1418 for (i = 0; i < CE_COUNT; i++) {
1419 pipe = &ar_snoc->pipe_info[i];
1420 pipe->ce_hdl = &ce->ce_states[i];
1421 pipe->pipe_num = i;
1422 pipe->hif_ce_state = ar;
1423
1424 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1425 if (ret) {
1426 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1427 i, ret);
1428 return ret;
1429 }
1430
1431 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max;
1432 }
1433 ath10k_snoc_init_napi(ar);
1434
1435 return 0;
1436 }
1437
ath10k_snoc_release_resource(struct ath10k * ar)1438 static void ath10k_snoc_release_resource(struct ath10k *ar)
1439 {
1440 int i;
1441
1442 netif_napi_del(&ar->napi);
1443 for (i = 0; i < CE_COUNT; i++)
1444 ath10k_ce_free_pipe(ar, i);
1445 }
1446
ath10k_msa_dump_memory(struct ath10k * ar,struct ath10k_fw_crash_data * crash_data)1447 static void ath10k_msa_dump_memory(struct ath10k *ar,
1448 struct ath10k_fw_crash_data *crash_data)
1449 {
1450 const struct ath10k_hw_mem_layout *mem_layout;
1451 const struct ath10k_mem_region *current_region;
1452 struct ath10k_dump_ram_data_hdr *hdr;
1453 size_t buf_len;
1454 u8 *buf;
1455
1456 if (!crash_data || !crash_data->ramdump_buf)
1457 return;
1458
1459 mem_layout = ath10k_coredump_get_mem_layout(ar);
1460 if (!mem_layout)
1461 return;
1462
1463 current_region = &mem_layout->region_table.regions[0];
1464
1465 buf = crash_data->ramdump_buf;
1466 buf_len = crash_data->ramdump_buf_len;
1467 memset(buf, 0, buf_len);
1468
1469 /* Reserve space for the header. */
1470 hdr = (void *)buf;
1471 buf += sizeof(*hdr);
1472 buf_len -= sizeof(*hdr);
1473
1474 hdr->region_type = cpu_to_le32(current_region->type);
1475 hdr->start = cpu_to_le32((unsigned long)ar->msa.vaddr);
1476 hdr->length = cpu_to_le32(ar->msa.mem_size);
1477
1478 if (current_region->len < ar->msa.mem_size) {
1479 memcpy_fromio(buf,
1480 (const void __iomem __force *)ar->msa.vaddr,
1481 current_region->len);
1482 ath10k_warn(ar, "msa dump length is less than msa size %x, %x\n",
1483 current_region->len, ar->msa.mem_size);
1484 } else {
1485 memcpy_fromio(buf,
1486 (const void __iomem __force *)ar->msa.vaddr,
1487 ar->msa.mem_size);
1488 }
1489 }
1490
ath10k_snoc_fw_crashed_dump(struct ath10k * ar)1491 void ath10k_snoc_fw_crashed_dump(struct ath10k *ar)
1492 {
1493 struct ath10k_fw_crash_data *crash_data;
1494 char guid[UUID_STRING_LEN + 1];
1495
1496 mutex_lock(&ar->dump_mutex);
1497
1498 spin_lock_bh(&ar->data_lock);
1499 ar->stats.fw_crash_counter++;
1500 spin_unlock_bh(&ar->data_lock);
1501
1502 crash_data = ath10k_coredump_new(ar);
1503
1504 if (crash_data)
1505 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1506 else
1507 scnprintf(guid, sizeof(guid), "n/a");
1508
1509 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1510 ath10k_print_driver_info(ar);
1511 ath10k_msa_dump_memory(ar, crash_data);
1512 mutex_unlock(&ar->dump_mutex);
1513 }
1514
ath10k_snoc_modem_notify(struct notifier_block * nb,unsigned long action,void * data)1515 static int ath10k_snoc_modem_notify(struct notifier_block *nb, unsigned long action,
1516 void *data)
1517 {
1518 struct ath10k_snoc *ar_snoc = container_of(nb, struct ath10k_snoc, nb);
1519 struct ath10k *ar = ar_snoc->ar;
1520 struct qcom_ssr_notify_data *notify_data = data;
1521
1522 switch (action) {
1523 case QCOM_SSR_BEFORE_POWERUP:
1524 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem starting event\n");
1525 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1526 break;
1527
1528 case QCOM_SSR_AFTER_POWERUP:
1529 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem running event\n");
1530 break;
1531
1532 case QCOM_SSR_BEFORE_SHUTDOWN:
1533 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem %s event\n",
1534 notify_data->crashed ? "crashed" : "stopping");
1535 if (!notify_data->crashed)
1536 set_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1537 else
1538 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1539 break;
1540
1541 case QCOM_SSR_AFTER_SHUTDOWN:
1542 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem offline event\n");
1543 break;
1544
1545 default:
1546 ath10k_err(ar, "received unrecognized event %lu\n", action);
1547 break;
1548 }
1549
1550 return NOTIFY_OK;
1551 }
1552
ath10k_modem_init(struct ath10k * ar)1553 static int ath10k_modem_init(struct ath10k *ar)
1554 {
1555 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1556 void *notifier;
1557 int ret;
1558
1559 ar_snoc->nb.notifier_call = ath10k_snoc_modem_notify;
1560
1561 notifier = qcom_register_ssr_notifier("mpss", &ar_snoc->nb);
1562 if (IS_ERR(notifier)) {
1563 ret = PTR_ERR(notifier);
1564 ath10k_err(ar, "failed to initialize modem notifier: %d\n", ret);
1565 return ret;
1566 }
1567
1568 ar_snoc->notifier = notifier;
1569
1570 return 0;
1571 }
1572
ath10k_modem_deinit(struct ath10k * ar)1573 static void ath10k_modem_deinit(struct ath10k *ar)
1574 {
1575 int ret;
1576 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1577
1578 ret = qcom_unregister_ssr_notifier(ar_snoc->notifier, &ar_snoc->nb);
1579 if (ret)
1580 ath10k_err(ar, "error %d unregistering notifier\n", ret);
1581 }
1582
ath10k_setup_msa_resources(struct ath10k * ar,u32 msa_size)1583 static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size)
1584 {
1585 struct device *dev = ar->dev;
1586 struct resource r;
1587 int ret;
1588
1589 ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &r);
1590 if (!ret) {
1591 ar->msa.paddr = r.start;
1592 ar->msa.mem_size = resource_size(&r);
1593 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr,
1594 ar->msa.mem_size,
1595 MEMREMAP_WT);
1596 if (IS_ERR(ar->msa.vaddr)) {
1597 dev_err(dev, "failed to map memory region: %pa\n",
1598 &r.start);
1599 return PTR_ERR(ar->msa.vaddr);
1600 }
1601 } else {
1602 ar->msa.vaddr = dmam_alloc_coherent(dev, msa_size,
1603 &ar->msa.paddr,
1604 GFP_KERNEL);
1605 if (!ar->msa.vaddr) {
1606 ath10k_err(ar, "failed to allocate dma memory for msa region\n");
1607 return -ENOMEM;
1608 }
1609 ar->msa.mem_size = msa_size;
1610 }
1611
1612 ath10k_dbg(ar, ATH10K_DBG_QMI, "qmi msa.paddr: %pad , msa.vaddr: 0x%p\n",
1613 &ar->msa.paddr,
1614 ar->msa.vaddr);
1615
1616 return 0;
1617 }
1618
ath10k_fw_init(struct ath10k * ar)1619 static int ath10k_fw_init(struct ath10k *ar)
1620 {
1621 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1622 struct device *host_dev = &ar_snoc->dev->dev;
1623 struct platform_device_info info;
1624 struct iommu_domain *iommu_dom;
1625 struct platform_device *pdev;
1626 struct device_node *node;
1627 int ret;
1628
1629 node = of_get_child_by_name(host_dev->of_node, "wifi-firmware");
1630 if (!node) {
1631 ar_snoc->use_tz = true;
1632 return 0;
1633 }
1634
1635 memset(&info, 0, sizeof(info));
1636 info.fwnode = &node->fwnode;
1637 info.parent = host_dev;
1638 info.name = node->name;
1639 info.dma_mask = DMA_BIT_MASK(32);
1640
1641 pdev = platform_device_register_full(&info);
1642 if (IS_ERR(pdev)) {
1643 of_node_put(node);
1644 return PTR_ERR(pdev);
1645 }
1646
1647 pdev->dev.of_node = node;
1648
1649 ret = of_dma_configure(&pdev->dev, node, true);
1650 if (ret) {
1651 ath10k_err(ar, "dma configure fail: %d\n", ret);
1652 goto err_unregister;
1653 }
1654
1655 ar_snoc->fw.dev = &pdev->dev;
1656
1657 iommu_dom = iommu_paging_domain_alloc(ar_snoc->fw.dev);
1658 if (IS_ERR(iommu_dom)) {
1659 ath10k_err(ar, "failed to allocate iommu domain\n");
1660 ret = PTR_ERR(iommu_dom);
1661 goto err_unregister;
1662 }
1663
1664 ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev);
1665 if (ret) {
1666 ath10k_err(ar, "could not attach device: %d\n", ret);
1667 goto err_iommu_free;
1668 }
1669
1670 ar_snoc->fw.iommu_domain = iommu_dom;
1671 ar_snoc->fw.fw_start_addr = ar->msa.paddr;
1672
1673 ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr,
1674 ar->msa.paddr, ar->msa.mem_size,
1675 IOMMU_READ | IOMMU_WRITE, GFP_KERNEL);
1676 if (ret) {
1677 ath10k_err(ar, "failed to map firmware region: %d\n", ret);
1678 goto err_iommu_detach;
1679 }
1680
1681 of_node_put(node);
1682
1683 return 0;
1684
1685 err_iommu_detach:
1686 iommu_detach_device(iommu_dom, ar_snoc->fw.dev);
1687
1688 err_iommu_free:
1689 iommu_domain_free(iommu_dom);
1690
1691 err_unregister:
1692 platform_device_unregister(pdev);
1693 of_node_put(node);
1694
1695 return ret;
1696 }
1697
ath10k_fw_deinit(struct ath10k * ar)1698 static int ath10k_fw_deinit(struct ath10k *ar)
1699 {
1700 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1701 const size_t mapped_size = ar_snoc->fw.mapped_mem_size;
1702 struct iommu_domain *iommu;
1703 size_t unmapped_size;
1704
1705 if (ar_snoc->use_tz)
1706 return 0;
1707
1708 iommu = ar_snoc->fw.iommu_domain;
1709
1710 unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr,
1711 mapped_size);
1712 if (unmapped_size != mapped_size)
1713 ath10k_err(ar, "failed to unmap firmware: %zu\n",
1714 unmapped_size);
1715
1716 iommu_detach_device(iommu, ar_snoc->fw.dev);
1717 iommu_domain_free(iommu);
1718
1719 platform_device_unregister(to_platform_device(ar_snoc->fw.dev));
1720
1721 return 0;
1722 }
1723
1724 static const struct of_device_id ath10k_snoc_dt_match[] = {
1725 { .compatible = "qcom,wcn3990-wifi",
1726 .data = &drv_priv,
1727 },
1728 { }
1729 };
1730 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match);
1731
ath10k_snoc_probe(struct platform_device * pdev)1732 static int ath10k_snoc_probe(struct platform_device *pdev)
1733 {
1734 const struct ath10k_snoc_drv_priv *drv_data;
1735 struct ath10k_snoc *ar_snoc;
1736 struct device *dev;
1737 struct ath10k *ar;
1738 u32 msa_size;
1739 int ret;
1740 u32 i;
1741
1742 dev = &pdev->dev;
1743 drv_data = device_get_match_data(dev);
1744 if (!drv_data) {
1745 dev_err(dev, "failed to find matching device tree id\n");
1746 return -EINVAL;
1747 }
1748
1749 ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask);
1750 if (ret) {
1751 dev_err(dev, "failed to set dma mask: %d\n", ret);
1752 return ret;
1753 }
1754
1755 ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC,
1756 drv_data->hw_rev, &ath10k_snoc_hif_ops);
1757 if (!ar) {
1758 dev_err(dev, "failed to allocate core\n");
1759 return -ENOMEM;
1760 }
1761
1762 ar_snoc = ath10k_snoc_priv(ar);
1763 ar_snoc->dev = pdev;
1764 platform_set_drvdata(pdev, ar);
1765 ar_snoc->ar = ar;
1766 ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
1767 ar->ce_priv = &ar_snoc->ce;
1768 msa_size = drv_data->msa_size;
1769
1770 ath10k_snoc_quirks_init(ar);
1771
1772 ret = ath10k_snoc_resource_init(ar);
1773 if (ret) {
1774 ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
1775 goto err_core_destroy;
1776 }
1777
1778 ret = ath10k_snoc_setup_resource(ar);
1779 if (ret) {
1780 ath10k_warn(ar, "failed to setup resource: %d\n", ret);
1781 goto err_core_destroy;
1782 }
1783 ret = ath10k_snoc_request_irq(ar);
1784 if (ret) {
1785 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
1786 goto err_release_resource;
1787 }
1788
1789 /*
1790 * devm_pwrseq_get() can return -EPROBE_DEFER in two cases:
1791 * - it is not supposed to be used
1792 * - it is supposed to be used, but the driver hasn't probed yet.
1793 *
1794 * There is no simple way to distinguish between these two cases, but:
1795 * - if it is not supposed to be used, then regulator_bulk_get() will
1796 * return all regulators as expected, continuing the probe
1797 * - if it is supposed to be used, but wasn't probed yet, we will get
1798 * -EPROBE_DEFER from regulator_bulk_get() too.
1799 *
1800 * For backwards compatibility with DTs specifying regulators directly
1801 * rather than using the PMU device, ignore the defer error from
1802 * pwrseq.
1803 */
1804 ar_snoc->pwrseq = devm_pwrseq_get(&pdev->dev, "wlan");
1805 if (IS_ERR(ar_snoc->pwrseq)) {
1806 ret = PTR_ERR(ar_snoc->pwrseq);
1807 ar_snoc->pwrseq = NULL;
1808 if (ret != -EPROBE_DEFER)
1809 goto err_free_irq;
1810
1811 ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators);
1812 } else {
1813 /*
1814 * The first regulator (vdd-0.8-cx-mx) is used to power on part
1815 * of the SoC rather than the PMU on WCN399x, the rest are
1816 * handled via pwrseq.
1817 */
1818 ar_snoc->num_vregs = 1;
1819 }
1820
1821 ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs,
1822 sizeof(*ar_snoc->vregs), GFP_KERNEL);
1823 if (!ar_snoc->vregs) {
1824 ret = -ENOMEM;
1825 goto err_free_irq;
1826 }
1827 for (i = 0; i < ar_snoc->num_vregs; i++)
1828 ar_snoc->vregs[i].supply = ath10k_regulators[i];
1829
1830 ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs,
1831 ar_snoc->vregs);
1832 if (ret < 0)
1833 goto err_free_irq;
1834
1835 ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks);
1836 ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks,
1837 sizeof(*ar_snoc->clks), GFP_KERNEL);
1838 if (!ar_snoc->clks) {
1839 ret = -ENOMEM;
1840 goto err_free_irq;
1841 }
1842
1843 for (i = 0; i < ar_snoc->num_clks; i++)
1844 ar_snoc->clks[i].id = ath10k_clocks[i];
1845
1846 ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks,
1847 ar_snoc->clks);
1848 if (ret)
1849 goto err_free_irq;
1850
1851 ret = ath10k_setup_msa_resources(ar, msa_size);
1852 if (ret) {
1853 ath10k_warn(ar, "failed to setup msa resources: %d\n", ret);
1854 goto err_free_irq;
1855 }
1856
1857 ret = ath10k_fw_init(ar);
1858 if (ret) {
1859 ath10k_err(ar, "failed to initialize firmware: %d\n", ret);
1860 goto err_free_irq;
1861 }
1862
1863 ret = ath10k_qmi_init(ar, msa_size);
1864 if (ret) {
1865 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret);
1866 goto err_fw_deinit;
1867 }
1868
1869 ret = ath10k_modem_init(ar);
1870 if (ret)
1871 goto err_qmi_deinit;
1872
1873 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n");
1874
1875 return 0;
1876
1877 err_qmi_deinit:
1878 ath10k_qmi_deinit(ar);
1879
1880 err_fw_deinit:
1881 ath10k_fw_deinit(ar);
1882
1883 err_free_irq:
1884 ath10k_snoc_free_irq(ar);
1885
1886 err_release_resource:
1887 ath10k_snoc_release_resource(ar);
1888
1889 err_core_destroy:
1890 ath10k_core_destroy(ar);
1891
1892 return ret;
1893 }
1894
ath10k_snoc_free_resources(struct ath10k * ar)1895 static int ath10k_snoc_free_resources(struct ath10k *ar)
1896 {
1897 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1898
1899 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc free resources\n");
1900
1901 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags);
1902
1903 ath10k_core_unregister(ar);
1904 ath10k_fw_deinit(ar);
1905 ath10k_snoc_free_irq(ar);
1906 ath10k_snoc_release_resource(ar);
1907 ath10k_modem_deinit(ar);
1908 ath10k_qmi_deinit(ar);
1909 ath10k_core_destroy(ar);
1910
1911 return 0;
1912 }
1913
ath10k_snoc_remove(struct platform_device * pdev)1914 static void ath10k_snoc_remove(struct platform_device *pdev)
1915 {
1916 struct ath10k *ar = platform_get_drvdata(pdev);
1917 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1918
1919 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n");
1920
1921 reinit_completion(&ar->driver_recovery);
1922
1923 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1924 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ);
1925
1926 ath10k_snoc_free_resources(ar);
1927 }
1928
ath10k_snoc_shutdown(struct platform_device * pdev)1929 static void ath10k_snoc_shutdown(struct platform_device *pdev)
1930 {
1931 struct ath10k *ar = platform_get_drvdata(pdev);
1932
1933 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc shutdown\n");
1934 ath10k_snoc_free_resources(ar);
1935 }
1936
1937 static struct platform_driver ath10k_snoc_driver = {
1938 .probe = ath10k_snoc_probe,
1939 .remove = ath10k_snoc_remove,
1940 .shutdown = ath10k_snoc_shutdown,
1941 .driver = {
1942 .name = "ath10k_snoc",
1943 .of_match_table = ath10k_snoc_dt_match,
1944 },
1945 };
1946 module_platform_driver(ath10k_snoc_driver);
1947
1948 MODULE_AUTHOR("Qualcomm");
1949 MODULE_LICENSE("Dual BSD/GPL");
1950 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");
1951