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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm4250-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM4250 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
18 const: qcom,sm4250-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
[all …]
H A Dqcom,sm8250-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
18 const: qcom,sm8250-lpass-lpi-pinctrl
25 - description: LPASS Core voting clock
26 - description: LPASS Audio voting clock
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H A Dqcom,sm8450-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
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H A Dqcom,mdm9615-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
12 description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
14 $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18 const: qcom,mdm9615-pinctrl
27 "-state$":
29 - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
[all …]
H A Dbitmain,bm1880-pinctrl.txt3 This binding describes the pin controller found in the BM1880 SoC.
7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17 includes pinmux and various pin configuration parameters, such as pull-up,
24 The following generic properties as defined in pinctrl-bindings.txt are valid
29 - pins: An array of strings, each string containing the name of a pin.
32 MIO0 - MIO111
34 - groups: An array of strings, each string containing the name of a pin
[all …]
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-sc7280-lpass-lpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * ALSA SoC platform-machine driver for QTi LPASS
11 #include "pinctrl-lpass-lpi.h"
50 PINCTRL_PIN(10, "gpio10"),
65 static const char * const i2s2_clk_groups[] = { "gpio10" };
75 static const char * const wsa_swr_clk_groups[] = { "gpio10" };
132 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
141 .name = "qcom-sc7280-lpass-lpi-pinctrl",
/linux/Documentation/devicetree/bindings/mfd/
H A Dbrcm,bcm6318-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6318 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
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H A Dbrcm,bcm6362-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6362 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
[all …]
H A Dbrcm,bcm6368-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6368 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dk3-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
28 /* SoC portion */
30 compatible = "hisilicon,hi4511-dw-mshc";
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019-ap.dk07.1-c1.dts1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include "qcom-ipq4019-ap.dk07.1.dtsi"
8 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
9 compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";
11 soc {
14 perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
22 serial_1_pins: serial1-state {
24 "gpio10", "gpio11";
26 bias-disable;
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H A Dqcom-ipq4019-ap.dk04.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
25 soc {
27 serial_0_pins: serial0-state {
30 bias-disable;
33 serial_1_pins: serial1-state {
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa320.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/pxa320.c
9 * 2007-08-21: eric miao <eric.miao@marvell.com>
17 #include <linux/soc/pxa/cpu.h>
28 MFP_ADDR(GPIO10, 0x0458),
H A Dmfp-pxa2xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/soc/pxa/mfp.h>
8 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
19 * bit 23 - Input/Output (PXA2xx specific)
20 * bit 24 - Wakeup Enable(PXA2xx specific)
21 * bit 25 - Keep Output (PXA2xx specific)
64 #define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0)
H A Dmfp-pxa3xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/soc/pxa/mfp.h>
9 /* PXA3xx common MFP configurations - processor specific ones defined
10 * in mfp-pxa300.h and mfp-pxa320.h
22 #define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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/linux/drivers/pinctrl/
H A Dpinctrl-lantiq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/drivers/pinctrl/pinctrl-lantiq.h
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
102 /* soc specific callback used to apply muxing */
117 GPIO10, /* 10 */ enumerator
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-ab8505.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
5 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
13 #include "pinctrl-abx500.h"
250 * ALTERNATFUNC register. We need to specifies these values as SOC
286 …ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by b…
345 * GPIO10 to GPIO11
377 abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) in abx500_pinctrl_ab8505_init() argument
379 *soc = &ab8505_soc; in abx500_pinctrl_ab8505_init()
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-nezha.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO
12 * Lines which are routed to the 40-pin header are named as follows:
15 * <pin#> is the actual pin number of the 40-pin header
20 * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
26 /dts-v1/;
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3670-hikey970.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
14 #include "hikey970-pinctrl.dtsi"
15 #include "hikey970-pmic.dtsi"
19 compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
34 stdout-path = "serial6:115200n8";
43 wlan_en: wlan-en-1-8v {
44 compatible = "regulator-fixed";
45 regulator-name = "wlan-en-regulator";
[all …]
/linux/arch/arm64/boot/dts/lg/
H A Dlg1312.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for lg1312 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a53";
[all …]
H A Dlg1313.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for lg1313 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a53";
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-href-ab8500.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "ste-ab8500.dtsi"
9 soc {
13 pinctrl-names = "default", "sleep";
14 pinctrl-0 = <&usb_a_1_default>;
15 pinctrl-1 = <&usb_a_1_sleep>;
20 regulator-name = "V-DISPLAY";
24 regulator-name = "V-eMMC1";
28 regulator-name = "V-MMC-SD";
32 regulator-name = "V-INTCORE";
[all …]
H A Dste-href-ab8505.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "ste-ab8505.dtsi"
9 soc {
13 pinctrl-names = "default", "sleep";
14 pinctrl-0 = <&usb_a_1_default>;
15 pinctrl-1 = <&usb_a_1_sleep>;
20 regulator-name = "V-DISPLAY";
24 regulator-name = "V-eMMC1";
28 regulator-name = "V-MMC-SD";
32 regulator-name = "V-INTCORE";
[all …]

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