| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | rcar_can.txt | 1 Renesas R-Car CAN controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC.
6 "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
7 "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC.
8 "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
9 "renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
10 "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
11 "renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
12 "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | renesas,sdhi.txt | 1 * Renesas SDHI SD/MMC controller
4 - compatible: should contain one or more of the following:
5 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
6 "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
7 "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
8 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
9 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
10 "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
11 "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
12 "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | gemini.txt | 3 The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
9 Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
13 Many of the IP blocks used in the SoC comes from Faraday Technology.
20 - soc: the SoC should be represented by a simple bus encompassing all the
21 onchip devices, this is referred to as the soc bus node.
23 - syscon: the soc bus node must have a system controller node pointing to the
25 "cortina,gemini-syscon", "syscon";
28 - reg: syscon register location and size.
29 - #clock-cells: should be set to <1> - the system controller is also a
31 - #reset-cells: should be set to <1> - the system controller is also a
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/soc/litex/ |
| H A D | litex,soc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/soc/lite
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | samsung,s3c2410-clock.txt | 1 * Samsung S3C2410 Clock Controller
3 The S3C2410 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to the s3c2410,
9 - compatible: should be one of the following.
10 - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
11 - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
12 - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
19 on a particular SoC.
[all …]
|
| H A D | samsung,s3c2443-clock.txt | 1 * Samsung S3C2443 Clock Controller
3 The S3C2443 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
19 on a particular SoC.
[all …]
|
| H A D | amlogic,gxbb-clkc.txt | 3 The Amlogic GXBB clock controller generates and supplies clock to various
4 controllers within the SoC.
8 - compatible: should be:
9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
12 "amlogic,g12a-clkc" for G12A SoC.
13 "amlogic,g12b-clkc" for G12B SoC.
14 "amlogic,sm1-clkc" for SM1 SoC.
15 - clocks : list of clock phandle, one for each entry clock-names.
[all …]
|
| H A D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
4 controller, which generates and supplies clock to various controllers
5 within the SoC.
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
13 S5P6442 SoC.
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
[all …]
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| H A D | exynos4-clock.txt | 1 * Samsung Exynos4 Clock Controller
3 The Exynos4 clock controller generates and supplies clock to various controllers
4 within the Exynos4 SoC. The clock binding described here is applicable to all
5 SoC's in the Exynos4 family.
9 - compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
22 dt-bindings/clock/exynos4.h header and can be used in device
[all …]
|
| H A D | rockchip,rk3128-cru.txt | 3 The RK3126/RK3128 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
12 - reg: physical base address of the controller and length of memory mapped
14 - #clock-cells: should be 1.
15 - #reset-cells: should be 1.
19 - rockchip,grf: phandle to the syscon managing the "general register files"
24 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
[all …]
|
| H A D | exynos3250-clock.txt | 1 * Samsung Exynos3250 Clock Controller
3 The Exynos3250 clock controller generates and supplies clock to various
4 controllers within the Exynos3250 SoC.
8 - compatible: should be one of the following.
9 - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
10 - "samsung,exynos3250-cmu-dmc" - controller compatible with
11 Exynos3250 SoC for Dynamic Memory Controller domain.
12 - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
13 with Exynos3250 SOC
15 - reg: physical base address of the controller and length of memory mapped
[all …]
|
| H A D | samsung,s3c64xx-clock.txt | 1 * Samsung S3C64xx Clock Controller
3 The S3C64xx clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
20 on a particular S3C64xx SoC and this is specified where applicable.
23 dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
[all …]
|
| H A D | exynos5420-clock.txt | 1 * Samsung Exynos5420 Clock Controller
3 The Exynos5420 clock controller generates and supplies clock to various
4 controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
8 - compatible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
12 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
21 dt-bindings/clock/exynos5420.h header and can be used in device
24 Example 1: An example of a clock controller node is listed below.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
|
| H A D | brcm,iproc-gpio.txt | 1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/soc/microchip/ |
| H A D | microchip,polarfire-soc-sys-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <conor.dooley@microchip.com>
13 The PolarFire SoC system controller is communicated with via a mailbox.
22 const: microchip,polarfire-soc-sys-controller
25 - compatible
26 - mboxes
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/ |
| H A D | hisilicon.txt | 2 ----------------------------------------------------
3 Hi3660 SoC
5 - compatible = "hisilicon,hi3660";
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
11 Hi3670 SoC
13 - compatible = "hisilicon,hi3670";
17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
19 Hi3798cv200 SoC
21 - compatible = "hisilicon,hi3798cv200";
25 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-mpc8xxx.txt | 1 * Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
4 - compatible : Should be "fsl,<soc>-gpio"
5 The following <soc>s are known to be supported:
8 - reg : Address and length of the register set for the device
9 - interrupts : Should be the port interrupt shared by all 32 pins.
10 - #gpio-cells : Should be two. The first cell is the pin number and
16 - little-endian : GPIO registers are used as little endian. If not
19 Example of gpio-controller node for a mpc5125 SoC:
22 compatible = "fsl,mpc5125-gpio";
23 #gpio-cells = <2>;
[all …]
|
| H A D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | samsung-phy.txt | 1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 System Controller
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Inc. Kendryte K210 SoC system controller which provides a
15 domains of the SoC.
20 - const: canaan,k210-sysctl
21 - const: syscon
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/soc/socionext/ |
| H A D | socionext,uniphier-soc-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | realtek,rtl-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL SoC interrupt controller
10 Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
13 All connected input lines from SoC peripherals can be masked individually,
18 - Birger Koblitz <mail@birger-koblitz.de>
19 - Bert Vermeulen <bert@biot.com>
20 - John Crispin <john@phrozen.org>
[all …]
|