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/linux/Documentation/devicetree/bindings/phy/
H A Dintel,keembay-phy-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
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/linux/drivers/phy/intel/
H A Dphy-intel-keembay-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
35 /* USS APB slave registers */
76 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_CLK_SET, in keembay_usb_clocks_on()
79 dev_err(priv->dev, "error clock set: %d\n", ret); in keembay_usb_clocks_on()
83 ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_RST_SET, in keembay_usb_clocks_on()
86 dev_err(priv->dev, "error reset set: %d\n", ret); in keembay_usb_clocks_on()
90 ret = regmap_update_bits(priv->regmap_slv, in keembay_usb_clocks_on()
95 dev_err(priv->dev, "error iddq disable: %d\n", ret); in keembay_usb_clocks_on()
102 ret = regmap_update_bits(priv->regmap_slv, USS_USB_PHY_CFG0, in keembay_usb_clocks_on()
106 dev_err(priv->dev, "error ref clock select: %d\n", ret); in keembay_usb_clocks_on()
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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