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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dintel,keembay-phy-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
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H A Dintel,phy-keembay-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,phy-keembay-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
14 const: intel,keembay-usb-phy
18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
21 reg-names:
23 - const: cpr-apb-base
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/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/freebsd/sys/riscv/starfive/
H A Djh7110_pcie.c2 * SPDX-License-Identifier: BSD-2-Clause
114 {"starfive,jh7110-pcie", 1},
161 #define RD4(sc, reg) bus_read_4((sc)->reg_mem_res, (reg))
162 #define WR4(sc, reg, val) bus_write_4((sc)->reg_mem_res, (reg), (val))
180 data = bus_read_1(sc->cfg_mem_res, offset); in jh7110_pcie_read_config()
183 data = le16toh(bus_read_2(sc->cfg_mem_res, offset)); in jh7110_pcie_read_config()
186 data = le32toh(bus_read_4(sc->cfg_mem_res, offset)); in jh7110_pcie_read_config()
211 bus_write_1(sc->cfg_mem_res, offset, val); in jh7110_pcie_write_config()
214 bus_write_2(sc->cfg_mem_res, offset, htole16(val)); in jh7110_pcie_write_config()
217 bus_write_4(sc->cfg_mem_res, offset, htole32(val)); in jh7110_pcie_write_config()
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