Home
last modified time | relevance | path

Searched +full:sink +full:- +full:wait +full:- +full:cap +full:- +full:time +full:- +full:ms (Results 1 – 7 of 7) sorted by relevance

/linux/net/ipv4/
H A Dtcp_bbr.c21 * +---> STARTUP ----+
24 * | DRAIN ----+
27 * +---> PROBE_BW ----+
30 * | +----+ |
32 * +---- PROBE_RTT <--+
37 * A long-lived BBR flow spends the vast majority of its time remaining
42 * it briefly enters PROBE_RTT to cut inflight to a minimum value to re-probe
43 * the path's two-way propagation delay (min_rtt). When exiting PROBE_RTT, if
48 * "BBR: Congestion-Based Congestion Control",
50 * Van Jacobson. ACM Queue, Vol. 14 No. 5, September-October 2016.
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019-2022 MediaTek Inc.
18 #include <linux/arm-smccc.h>
23 #include <linux/media-bus-format.h>
24 #include <linux/nvmem-consumer.h>
33 #include <sound/hdmi-codec.h>
402 .name = "mtk-dp-registers",
415 ret = regmap_read(mtk_dp->regs, offset, &read_val); in mtk_dp_read()
417 dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n", in mtk_dp_read()
427 int ret = regmap_write(mtk_dp->regs, offset, val); in mtk_dp_write()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.c96 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
118 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
130 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
138 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
142 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
146 * rate -> channel coding.
154 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
168 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); in max_dprx_rate()
170 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
176 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); in max_dprx_lane_count()
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
45 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
102 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
103 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
750 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
954 /* The follow-up are derived from the above. We must ensure that it
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
[all …]
/linux/sound/pci/hda/
H A Dpatch_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
176 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
178 * Non-generic VIA/NVIDIA specific
[all …]
/linux/include/linux/platform_data/
H A Dcros_ec_commands.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
52 * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
77 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
78 #define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
79 #define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
81 #define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
82 #define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
83 #define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
84 #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
[all …]