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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Drenesas,isp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car ISP Channel Selector
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car ISP Channel Selector provides MIPI CSI-2 VC and DT filtering
15 capabilities for the Renesas R-Car family of devices. It is used in
16 conjunction with the R-Car VIN and CSI-2 modules, which provides the video
22 - enum:
23 - renesas,r8a779a0-isp # V3U
[all …]
H A Dmicrochip,csi2dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 CSI2DC - Camera Serial Interface 2 Demux Controller
27 accessible as a DMA slave port to a DMA controller.
29 CSI2DC supports a single 'port' node as a sink port with either Synopsys
30 32-bit IDI interface or a parallel interface.
32 CSI2DC supports one 'port' node as source port with parallel interface.
34 This port has an 'endpoint' that can be connected to a sink port of another
[all …]
/freebsd/share/man/man4/
H A Dsk.415 .\" 4. Neither the name of the author nor the names of any co-contributors
36 .Nd "SysKonnect SK-984x and SK-982x PCI Gigabit Ethernet adapter driver"
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
55 driver provides support for the SysKonnect SK-984x and SK-982x series PCI
65 allowing dual-port NIC configurations.
67 The SK-982x 1000baseT adapters also include a Broadcom BCM5400 1000baseTX
69 The Broadcom PHY is connected to the XMAC via its GMII port.
73 driver configures dual port SysKonnect adapters such that each XMAC
79 second port on dual port adapters for failover purposes: if the link
[all …]
H A Dproto.438 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
51 .Bd -ragged -offset indent
62 Programs can open these device special files and perform register-level
72 Especially hardware diagnostics requires a somewhat user-friendly interface
75 .Ss I/O port resources
76 Device special files created for I/O port resources allow
87 system calls are used to perform input and output (resp.) on the port.
88 The amount of data that can be read or written at any single time is either
97 system call is used to select the port number, relative to the I/O port
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dthine,thc63lvd1024.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 streams to parallel data outputs. The chip supports single/dual input/output
19 Single or dual operation mode, output data mapping and DDR output modes are
30 The device can operate in single or dual input and output modes.
32 When operating in single input mode, all pixels are received on port@0,
33 and port@1 shall not contain any endpoint. In dual input mode,
[all …]
H A Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
38 port@0:
[all …]
H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
[all …]
H A Dsimple-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Transparent non-programmable DRM bridges
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11 - Maxime Ripard <mripard@kernel.org>
14 This binding supports transparent non-programmable bridges that don't require
15 any configuration, with a single input and a single output.
20 - items:
[all …]
/freebsd/sys/dev/sfxge/common/
H A Def10_tlv_layout.h1 /*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
48 * systems which are little-endian and do not do strange things with structure
49 * padding. (Big-endian host systems will require some byte-swapping.)
51 * -----
53 * Please refer to SF-108797-SW for a general overview of the TLV partition
56 * -----
62 * - L is a location, indicating where this tag is expected to be found:
69 * - TTT is a type, which is just a unique value. The same type value
73 * - NNNN is an index of some form. Some item types are per-port, some
[all …]
/freebsd/sbin/ipf/ipnat/
H A Dipnat.54 ipnat, ipnat.conf \- IPFilter NAT file format
18 address, and optionally port number, will be specified.
22 by some stanzas to match a packet, followed by a "->" and this is then
28 to text that appears before the "->" and the "right hand side" (RHS) for text
37 map $nif 0/0 -> 0/32
43 map ppp0 0/0 -> 0/32
56 rules. Both the source address and optionally port number can be changed
62 map le0 0/0 -> 0/32
72 map le0 0/0 -> 0/0
79 map le0 10.1.1.0/24 -> 192.168.55.3/32
[all …]
/freebsd/tools/tools/netmap/
H A Dpkt-gen.81 .\" Copyright (c) 2016, George V. Neville-Neil
30 .Nm pkt-gen
34 .Bl -item -compact
43 .Op Fl d Ar dst_ip[:port[-dst_ip:port]]
44 .Op Fl s Ar src_ip[:port[-src_ip:port]]
65 .Bl -tag -width Ds
75 port (e.g., valeSSS:PPP), the name of a netmap pipe or monitor,
76 or any valid netmap port name accepted by the
90 for client-side ping-pong operation, and
92 for server-side ping-pong operation.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid0
[all...]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-port
[all...]
H A Drenesas,rza1-pinctrl.txt5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
6 writing configuration values to per-port register sets.
7 Each "port" features up to 16 pins, each of them configurable for GPIO
8 function (port mode) or in alternate function mode.
9 Up to 8 different alternate function modes exist for each single pin.
12 -------------------
15 - compatible: should be:
16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
18 - "renesas,r7s72102-ports": for RZ/A1L
[all …]
H A Drenesas,rza2-pinctrl.txt4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
5 Each port features up to 8 pins, each of them configurable for GPIO
6 function (port mode) or in alternate function mode.
7 Up to 8 different alternate function modes exist for each single pin.
10 -------------------
13 - compatible: shall be:
14 - "renesas,r7s9210-pinctrl": for RZ/A2M
15 - reg
18 - gpio-controller
20 - #gpio-cells
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Ddraak.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
21 audio_clkout: audio-clkout {
24 * but needed to avoid cs2000/rcar_sound probe dead-lock
26 compatible = "fixed-clock";
27 #clock-cell
[all...]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dnvidia,tegra186-gpio.txt15 register set. These registers exist in a single contiguous block of physical
31 implemented by the SoC. Each GPIO is assigned to a port, and a port may control
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
33 name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
37 implemented GPIOs within each port varies. GPIO registers within a controller
38 are grouped and laid out according to the port they affect.
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-panda-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/
5 #include <dt-bindings/input/input.h>
7 #include "omap4-mcpdm.dtsi"
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
20 dsp_memory_region: dsp-memory@98000000 {
21 compatible = "shared-dma-pool";
27 ipu_memory_region: ipu-memory@98800000 {
[all …]
H A Dam57xx-sbc-am57x.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for CompuLab SBC-AM57x single board computer
5 * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/
9 #include "am57xx-cl-som-am57x.dts"
10 #include "compulab-sb-som.dtsi"
13 model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
14 …compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", …
23 uart3_pins_default: uart3-default-pins {
24 pinctrl-single,pins = <
30 mmc1_pins_default: mmc1-default-pins {
[all …]
H A Domap3-beagle-xm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap3";
15 cpu0-supply = <&vcc>;
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <26000000>;
37 led-controller-1 {
38 compatible = "gpio-leds";
[all …]
H A Dmotorola-mapphone-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "motorola-cpcap-mapphone.dtsi"
10 * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
11 * then 1023 - 102
[all...]
/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_qos_parser_l.l3 * Copyright (c) 2004-2006 Voltaire, Inc. All rights reserved.
4 * Copyright (c) 2002-2008 Mellanox Technologies LTD. All rights reserved.
5 * Copyright (c) 1996-2003 Intel Corporation. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
78 #define START_PORT_GUID {in_list_of_hex_num_ranges = TRUE;} /* comma-separated list of hex num…
79 #define START_PORT_NAME {in_list_of_strings = TRUE;} /* comma-separated list of following stri…
80 #define START_PARTITION {in_single_string = TRUE;} /* single string w/o whitespaces (partiti…
81 #define START_NAME {in_single_string = TRUE;} /* single string w/o whitespaces (port gr…
82 #define START_QOS_LEVEL_NAME {in_single_string = TRUE;} /* single string w/o whitespaces (qos lev…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dsrio.txt3 RapidIO port node:
5 - compatible
11 Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
15 - reg
17 Value type: <prop-encoded-array>
22 - interrupts
24 Value type: <prop_encoded-array>
30 A single IRQ that handles error conditions is specified by this
31 property. (Typically shared with port-write).
33 - fsl,srio-rmu-handle:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-common-dual.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common-dual.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Dual-Link Display Panels
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 support also single link.
18 - $ref: panel-common.yaml#
26 port@0:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dhisilicon-hns-nic.txt4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
11 connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
20 +-+-+-+---+-+-+-+-+-+-+
[all …]

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