| /linux/Documentation/devicetree/bindings/arm/omap/ |
| H A D | ctrl.txt | 11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
15 - compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-scm"
21 "ti,omap3-scm"
22 "ti,omap4-scm-core"
23 "ti,omap4-scm-padconf-core"
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 105 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
108 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
111 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
114 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
117 …This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
120 … This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
123 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
126 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
129 …ta cache entering write streaming mode.This event counts for each entry into write-streaming mode",
132 …ata cache entering write streaming mode.This event counts for each entry into write-streaming mode"
[all …]
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
[all …]
|
| H A D | xilinx-xadc.txt | 16 communication. Xilinx provides a standard IP core that can be used to access the
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
28 Xilinx System Management Wizard fabric IP core to access the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
[all …]
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| H A D | ti,ads1119.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com>
13 The TI ADS1119 is a precision 16-bit ADC over I2C that offers single-ended and
28 reset-gpios:
31 avdd-supply: true
32 dvdd-supply: true
34 vref-supply:
38 "#address-cells":
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 102 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L…
105 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L…
114 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
117 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
126 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami…
129 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami…
132 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami…
135 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami…
138 …el cache write streaming mode. This event counts for each cycle where the core is in write streami…
141 …el cache write streaming mode. This event counts for each cycle where the core is in write streami…
[all …]
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 AM62 SoC family support a single R5F core only which runs Device Manager
[all …]
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| /linux/drivers/gpu/drm/imagination/ |
| H A D | pvr_rogue_fwif_client.h | 1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
22 * Base page size is dependent on core:
27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
51 /* Use single core in a multi core setup. */
58 /* Use single core in a multi core setup. */
78 /*!< Use single core in a multi core setup. */
85 /*!< Use single core in a multi core setup. */
252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */
254 /* Stride IN BYTES for S-Buffer in case of RTAs. */
[all …]
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| /linux/Documentation/arch/x86/ |
| H A D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
28 the past a socket always contained a single package (see below), but with the
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - topology_num_threads_per_package()
[all …]
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| /linux/drivers/staging/media/atomisp/ |
| H A D | notes.txt | 6 The ISP has its own address-space and main memory needs to be mapped into
11 the hmm code finds the backing hmm-buffer-object (hmm_bo) by looking
25 So in this case a single binary handles the entire pipeline.
29 on the ISP can do multiple processing steps in a single pipeline
30 element (in a single binary).
36 the core atomisp code. The most important parts of the struct
37 are filled by the atomisp core itself, like e.g. the port number.
40 -metadata_width, metadata_height, metadata_effective_width, set by
41 the ov5693 driver (and used by the atomisp core)
42 -raw_bayer_order, adjusted by the ov2680 driver when flipping since
|
| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
[all …]
|
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
117 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
120 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
123 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
126 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
141 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
144 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
147 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
150 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
[all …]
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| /linux/include/media/ |
| H A D | tuner.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * tuner.h - definition for different tuners
5 * Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de)
6 * minor modifications by Ralph Metzler (rjkm@thp.uni-koeln.de)
14 #include <media/v4l2-mc.h>
73 #define TUNER_PHILIPS_4IN1 44 /* ATI TV Wonder Pro - Conexant */
83 #define TUNER_MICROTUNE_4042FI5 49 /* DViCO FusionHDTV 3 Gold-Q - 4042 FI5 (3X 8147) */
90 #define TUNER_TCL_2002MB 55 /* Hauppauge PVR-150 PAL */
92 #define TUNER_PHILIPS_FQ1216AME_MK4 56 /* Hauppauge PVR-150 PAL */
93 #define TUNER_PHILIPS_FQ1236A_MK4 57 /* Hauppauge PVR-500MCE NTSC */
[all …]
|
| /linux/drivers/hwspinlock/ |
| H A D | hwspinlock_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
7 * Contact: Ohad Ben-Cohen <ohad@wizery.com>
19 * struct hwspinlock_ops - platform-specific hwspinlock handlers
21 * @trylock: make a single attempt to take the lock. returns 0 on
24 * @bust: optional, platform-specific bust handler, called by hwspinlock
25 * core to bust a specific lock.
26 * @relax: optional, platform-specific relax handler, called by hwspinlock
27 * core while spinning on a lock, between two successive
38 * struct hwspinlock - this struct represents a single hwspinlock instance
[all …]
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| /linux/Documentation/networking/device_drivers/ethernet/chelsio/ |
| H A D | cxgb.rst | 1 .. SPDX-License-Identifier: GPL-2.0
35 Adaptive Interrupts (adaptive-rx)
36 ---------------------------------
46 By default, adaptive-rx is disabled.
47 To enable adaptive-rx::
49 ethtool -C <interface> adaptive-rx on
51 To disable adaptive-rx, use ethtool::
53 ethtool -C <interface> adaptive-rx off
55 After disabling adaptive-rx, the timer latency value will be set to 50us.
56 You may set the timer latency after disabling adaptive-rx::
[all …]
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
[all …]
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| /linux/drivers/remoteproc/ |
| H A D | xlnx_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
60 * struct zynqmp_sram_bank - sram bank description
[all …]
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| /linux/include/linux/ |
| H A D | stop_machine.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * stop_cpu[s]() is simplistic per-cpu maximum priority cpu
12 * monopolization mechanism. The caller can specify a non-sleeping
13 * function to be executed on a single or multiple cpus preempting all
25 struct list_head list; /* cpu_stopper->works */
54 int ret = -ENOENT; in stop_one_cpu()
67 stwork->fn(stwork->arg); in stop_one_cpu_nowait_workfn()
76 INIT_WORK(&work_buf->work, stop_one_cpu_nowait_workfn); in stop_one_cpu_nowait()
77 work_buf->fn = fn; in stop_one_cpu_nowait()
78 work_buf->arg = arg; in stop_one_cpu_nowait()
[all …]
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| /linux/Documentation/sound/designs/ |
| H A D | tracepoints.rst | 8 Tracepoints in ALSA PCM core
11 ALSA PCM core registers ``snd_pcm`` subsystem to kernel tracepoint system.
19 ------------------------------------
25 -----------------------------------------------------
30 In a design of ALSA PCM core, data transmission is abstracted as PCM substream.
34 interaction between applications and ALSA PCM core. Once decided, runtime of
46 Configurable. ALSA PCM core and some drivers handle this flag to select
53 - SNDRV_PCM_HW_PARAM_ACCESS
54 - SNDRV_PCM_HW_PARAM_FORMAT
55 - SNDRV_PCM_HW_PARAM_SUBFORMAT
[all …]
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| /linux/drivers/mmc/core/ |
| H A D | sdio_io.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/core/sdio_io.c
5 * Copyright 2007-2008 Pierre Ossman
16 #include "core.h"
21 * sdio_claim_host - exclusively claim a bus for a certain SDIO function
32 mmc_claim_host(func->card->host); in sdio_claim_host()
37 * sdio_release_host - release a bus for a certain SDIO function
48 mmc_release_host(func->card->host); in sdio_release_host()
53 * sdio_enable_func - enables a SDIO function for usage
66 return -EINVAL; in sdio_enable_func()
[all …]
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | adi,adin1110.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
15 an Ethernet PHY core with a MAC and all the associated analog
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
22 with the IEEE 802.3cg-2019 Ethernet standard for long reach
[all …]
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| /linux/tools/perf/pmu-events/ |
| H A D | README | 9 tree tools/perf/pmu-events/arch/foo.
11 - Regular files with '.json' extension in the name are assumed to be
14 - The CSV file that maps a specific CPU to its set of PMU events is to
17 - Directories are traversed, but all other files are ignored.
19 - To reduce JSON event duplication per architecture, platform JSONs may
26 such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic
27 should be placed in a separate JSON file - where the file name identifies
28 the topic. Eg: "Floating-point.json".
33 $ ls tools/perf/pmu-events/arch/x86/silvermont
34 cache.json memory.json virtual-memory.json
[all …]
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| /linux/fs/squashfs/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SquashFS 4.0 - Squashed file system support"
7 Read-Only File System). Squashfs is a highly compressed read-only
16 Squashfs is intended for general read-only filesystem use, for
19 and tools are available from github.com/plougher/squashfs-tools.
53 on the single buffer.
88 decompression. Each one exhibits various trade-offs between
91 If in doubt, select "Single threaded compression"
94 bool "Single threaded compression"
97 Traditionally Squashfs has used single-threaded decompression.
[all …]
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| /linux/arch/arm/boot/dts/st/ |
| H A D | st-pincfg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
29 /* User-frendly defines for Pin Direction */
49 * single-edge data non inverted clock, retime data with clk
54 * single-edge data inverted clock, retime data with clk
59 * double-edge data, retime data with clk
64 * Retiming the clk pins will park clock & reduce the noise within the core.
68 * CLK0, CLK1 modes with non-inverted clock
69 * Retiming the clk pins will park clock & reduce the noise within the core.
|