| /linux/Documentation/devicetree/bindings/arm/omap/ |
| H A D | ctrl.txt | 11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
15 - compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-scm"
21 "ti,omap3-scm"
22 "ti,omap4-scm-core"
23 "ti,omap4-scm-padconf-core"
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 105 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
108 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
111 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
114 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
117 …This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
120 … This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
123 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
126 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
129 …ta cache entering write streaming mode.This event counts for each entry into write-streaming mode",
132 …ata cache entering write streaming mode.This event counts for each entry into write-streaming mode"
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
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| H A D | xilinx-xadc.txt | 16 communication. Xilinx provides a standard IP core that can be used to access the
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
28 Xilinx System Management Wizard fabric IP core to access the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 102 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L…
105 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L…
114 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
117 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
126 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami…
129 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami…
132 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami…
135 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami…
138 …el cache write streaming mode. This event counts for each cycle where the core is in write streami…
141 …el cache write streaming mode. This event counts for each cycle where the core is in write streami…
[all …]
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 AM62 SoC family support a single R5F core only which runs Device Manager
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| /linux/drivers/gpu/drm/imagination/ |
| H A D | pvr_rogue_fwif_client.h | 1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
22 * Base page size is dependent on core:
27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
51 /* Use single core in a multi core setup. */
58 /* Use single core in a multi core setup. */
78 /*!< Use single core in a multi core setup. */
85 /*!< Use single core in a multi core setup. */
252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */
254 /* Stride IN BYTES for S-Buffer in case of RTAs. */
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| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
7 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
12 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
16 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
21 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
25 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
34 …core's cache, after the data is forwarded back to the requestor and indicating the data was found …
43 …core's caches, after the data is forwarded back to the requestor, and indicating the data was foun…
52 …core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Ex…
61 … was not found (IHitI) in this core's caches. A single snoop response from the core counts on all …
[all …]
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| /linux/drivers/staging/media/atomisp/ |
| H A D | notes.txt | 6 The ISP has its own address-space and main memory needs to be mapped into
11 the hmm code finds the backing hmm-buffer-object (hmm_bo) by looking
25 So in this case a single binary handles the entire pipeline.
29 on the ISP can do multiple processing steps in a single pipeline
30 element (in a single binary).
36 the core atomisp code. The most important parts of the struct
37 are filled by the atomisp core itself, like e.g. the port number.
40 -metadata_width, metadata_height, metadata_effective_width, set by
41 the ov5693 driver (and used by the atomisp core)
42 -raw_bayer_order, adjusted by the ov2680 driver when flipping since
|
| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
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|
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
117 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
120 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
123 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
126 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
141 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
144 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
147 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
150 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
[all …]
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| /linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
17 The bottom hierarchy level sits at core or thread level depending on whether
18 symmetric multi-threading (SMT) is supported or not.
23 in the system and map to the hierarchy level "core" above.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | apple,aic2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
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| /linux/include/media/ |
| H A D | tuner.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * tuner.h - definition for different tuners
5 * Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de)
6 * minor modifications by Ralph Metzler (rjkm@thp.uni-koeln.de)
14 #include <media/v4l2-mc.h>
73 #define TUNER_PHILIPS_4IN1 44 /* ATI TV Wonder Pro - Conexant */
83 #define TUNER_MICROTUNE_4042FI5 49 /* DViCO FusionHDTV 3 Gold-Q - 4042 FI5 (3X 8147) */
90 #define TUNER_TCL_2002MB 55 /* Hauppauge PVR-150 PAL */
92 #define TUNER_PHILIPS_FQ1216AME_MK4 56 /* Hauppauge PVR-150 PAL */
93 #define TUNER_PHILIPS_FQ1236A_MK4 57 /* Hauppauge PVR-500MCE NTSC */
[all …]
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | ite,it66121.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Phong LE <ple@baylibre.com>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The IT66121 is a high-performance and low-power single channel HDMI
21 - ite,it66121
22 - ite,it6610
27 reset-gpios:
31 vrf12-supply:
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| /linux/Documentation/networking/device_drivers/ethernet/chelsio/ |
| H A D | cxgb.rst | 1 .. SPDX-License-Identifier: GPL-2.0
35 Adaptive Interrupts (adaptive-rx)
36 ---------------------------------
46 By default, adaptive-rx is disabled.
47 To enable adaptive-rx::
49 ethtool -C <interface> adaptive-rx on
51 To disable adaptive-rx, use ethtool::
53 ethtool -C <interface> adaptive-rx off
55 After disabling adaptive-rx, the timer latency value will be set to 50us.
56 You may set the timer latency after disabling adaptive-rx::
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| /linux/drivers/hwspinlock/ |
| H A D | hwspinlock_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
7 * Contact: Ohad Ben-Cohen <ohad@wizery.com>
19 * struct hwspinlock_ops - platform-specific hwspinlock handlers
21 * @trylock: make a single attempt to take the lock. returns 0 on
24 * @bust: optional, platform-specific bust handler, called by hwspinlock
25 * core to bust a specific lock.
26 * @relax: optional, platform-specific relax handler, called by hwspinlock
27 * core while spinning on a lock, between two successive
38 * struct hwspinlock - this struct represents a single hwspinlock instance
[all …]
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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| /linux/drivers/remoteproc/ |
| H A D | xlnx_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
60 * struct zynqmp_sram_bank - sram bank description
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| /linux/Documentation/sound/designs/ |
| H A D | tracepoints.rst | 8 Tracepoints in ALSA PCM core
11 ALSA PCM core registers ``snd_pcm`` subsystem to kernel tracepoint system.
19 ------------------------------------
25 -----------------------------------------------------
30 In a design of ALSA PCM core, data transmission is abstracted as PCM substream.
34 interaction between applications and ALSA PCM core. Once decided, runtime of
46 Configurable. ALSA PCM core and some drivers handle this flag to select
53 - SNDRV_PCM_HW_PARAM_ACCESS
54 - SNDRV_PCM_HW_PARAM_FORMAT
55 - SNDRV_PCM_HW_PARAM_SUBFORMAT
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| /linux/fs/squashfs/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SquashFS 4.0 - Squashed file system support"
7 Read-Only File System). Squashfs is a highly compressed read-only
16 Squashfs is intended for general read-only filesystem use, for
19 and tools are available from github.com/plougher/squashfs-tools.
53 on the single buffe
[all...] |
| /linux/drivers/mmc/core/ |
| H A D | sdio_io.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/core/sdio_io.c
5 * Copyright 2007-2008 Pierre Ossman
16 #include "core.h"
21 * sdio_claim_host - exclusively claim a bus for a certain SDIO function
32 mmc_claim_host(func->card->host); in sdio_claim_host()
37 * sdio_release_host - release a bus for a certain SDIO function
48 mmc_release_host(func->card->host); in sdio_release_host()
53 * sdio_enable_func - enables a SDIO function for usage
66 return -EINVAL; in sdio_enable_func()
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| /linux/Documentation/networking/ |
| H A D | scaling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
[all …]
|