| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_dev.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
87 * Supplied by chip level and returned by the chip entry function xxx_identify,
93 * initialize &komeda_dev->format_table, this function should be called
100 * for CHIP to report or add pipeline and component resources to CORE
103 /** @cleanup: call to chip to cleanup komeda_dev->chip data */
112 * for CORE to get the HW event from the CHIP when interrupt happened.
139 * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
141 * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
142 * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
143 * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
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| /linux/drivers/irqchip/ |
| H A D | irq-aspeed-i2c-ic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2017 ASPEED Technology Inc.
28 * The aspeed chip provides a single hardware interrupt for all of the I2C
29 * busses, so we use a dummy interrupt chip to translate this single interrupt
30 * into multiple interrupts, each associated with a single I2C bus.
35 struct irq_chip *chip = irq_desc_get_chip(desc); in aspeed_i2c_ic_irq_handler() local
38 chained_irq_enter(chip, desc); in aspeed_i2c_ic_irq_handler()
39 status = readl(i2c_ic->base); in aspeed_i2c_ic_irq_handler()
41 generic_handle_domain_irq(i2c_ic->irq_domain, bit); in aspeed_i2c_ic_irq_handler()
43 chained_irq_exit(chip, desc); in aspeed_i2c_ic_irq_handler()
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| /linux/Documentation/hwmon/ |
| H A D | pcf8591.rst | 17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
35 - mode 1 : three differential inputs
39 - mode 2 : single ended and differential mixed
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| H A D | ads7828.rst | 6 * Texas Instruments/Burr-Brown ADS7828
23 - Steve Hardy <shardy@redhat.com>
24 - Vivien Didelot <vivien.didelot@savoirfairelinux.com>
25 - Guillaume Roguez <guillaume.roguez@savoirfairelinux.com>
28 -------------
34 set to true for differential mode, false for default single ended mode.
43 bounded with limits accepted by the chip, described in the datasheet.
45 If no structure is provided, the configuration defaults to single ended
49 -----------
53 The ADS7828 device is a 12-bit 8-channel A/D converter, while the ADS7830 does
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| H A D | submitting-patches.rst | 10 ----------
14 - Documentation/process/submit-checklist.rst
15 - Documentation/process/submitting-patches.rst
16 - Documentation/process/coding-style.rst
18 * Please run your patch through 'checkpatch --strict'. There should be no
22 * Please use the standard multi-line comment style. Do not mix C and C++
23 style comments in a single driver (with the exception of the SPDX license
34 hardware. In such cases, you should test-build the code on at least one
35 architecture. If run-time testing was not achieved, it should be written
43 -------------------------------------------
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| /linux/Documentation/devicetree/bindings/hwmon/ |
| H A D | ti,ina3221.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jean Delvare <jdelvare@suse.com>
11 - Guenter Roeck <linux@roeck-us.net>
20 ti,single-shot:
22 This chip has two power modes: single-shot (chip takes one measurement
23 and then shuts itself down) and continuous (chip takes continuous
25 hardware monitor type device, but the single-shot mode is more power-
26 friendly and useful for battery-powered device which cares power
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 Simple transparent bridge that is used by several non-DRM drivers to
36 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
43 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
67 ChromeOS EC ANX7688 is an ultra-low power
68 4K Ultra-HD (4096x2160p60) mobile HD transmitter
70 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
77 Driver for display connectors with support for DDC and hot-plug
81 on ARM-based platforms. Saying Y here when this driver is not needed
91 Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
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| /linux/kernel/irq/ |
| H A D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
48 * If the underlying implementation uses a single HW irq on in irq_reserve_ipi()
49 * all cpus then we only need a single Linux irq number for in irq_reserve_ipi()
74 return -EINVAL; in irq_reserve_ipi()
78 virq = irq_domain_alloc_descs(-1, nr_irqs, 0, NUMA_NO_NODE, NULL); in irq_reserve_ipi()
81 return -ENOMEM; in irq_reserve_ipi()
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| H A D | generic-chip.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Library implementing the most common irq chip callback functions
22 * irq_gc_noop - NOOP function
31 * irq_gc_mask_disable_reg - Mask chip via disable register
34 * Chip has separate enable/disable registers instead of a single mask
41 u32 mask = d->mask; in irq_gc_mask_disable_reg()
44 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
45 *ct->mask_cache &= ~mask; in irq_gc_mask_disable_reg()
51 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
54 * Chip has a single mask register. Values of this register are cached
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| /linux/drivers/regulator/ |
| H A D | da9121-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 // DA9121 Single-channel dual-phase 10A buck converter
7 // DA9130 Single-channel dual-phase 10A buck converter (Automotive)
8 // DA9217 Single-channel dual-phase 6A buck converter
9 // DA9122 Dual-channel single-phase 5A buck converter
10 // DA9131 Dual-channel single-phase 5A buck converter (Automotive)
11 // DA9220 Dual-channel single-phase 3A buck converter
12 // DA9132 Dual-channel single-phase 3A buck converter (Automotive)
29 #include "da9121-regulator.h"
31 /* Chip data */
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
64 the netlink mechanism. User-space applications can subscribe to these events
65 for real-time updates on various regulator events.
75 They provide two I2C-controlled DC/DC step-down converters with
101 tristate "Active-semi act8865 voltage regulator"
106 This driver controls a active-semi act8865 voltage output
110 tristate "Active-semi ACT8945A voltage regulator"
113 This driver controls a active-semi ACT8945A voltage regulator
114 via I2C bus. The ACT8945A features three step-down DC/DC converters
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| /linux/drivers/net/wireless/ti/wl12xx/ |
| H A D | wl12xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 /* WiLink 6/7 chip IDs */
19 /* FW chip version for wl127x */
21 /* minimum single-role FW version for wl127x */
26 /* minimum multi-role FW version for wl127x */
32 /* FW chip version for wl128x */
34 /* minimum single-role FW version for wl128x */
39 /* minimum multi-role FW version for wl128x */
127 * A bitmap (where each bit represents a single HLID)
133 * A bitmap (where each bit represents a single HLID) to indicate
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| /linux/Documentation/devicetree/bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | renesas,rcar-gyroadc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car GyroADC
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
15 are sampled by the GyroADC block in a round-robin fashion and the result
23 - enum:
24 - renesas,r8a7791-gyroadc
25 - renesas,r8a7792-gyroadc
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| /linux/include/linux/gpio/ |
| H A D | machine.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 * struct gpiod_lookup - lookup table
23 * @key: either the name of the chip the GPIO belongs to, or the GPIO line name
26 * @chip_hwnum: hardware number (i.e. relative to the chip) of the GPIO, or
50 * struct gpiod_hog - GPIO line hog table
51 * @chip_label: name of the chip the GPIO belongs to
52 * @chip_hwnum: hardware number (i.e. relative to the chip) of the GPIO
67 * Helper for lookup tables with just one single lookup for a device.
79 * Simple definition of a single GPIO under a con_id
99 * Simple definition of a single GPIO hog in an array.
|
| /linux/drivers/pinctrl/renesas/ |
| H A D | pinctrl-rza2.c | 1 // SPDX-License-Identifier: GPL-2.0
26 #define DRIVER_NAME "pinctrl-rza2"
55 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
56 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
57 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
58 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
59 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
60 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
62 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
63 #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
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| /linux/Documentation/devicetree/bindings/mux/ |
| H A D | mux-consumer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
19 mux-ctrl-specifier : array of #mux-control-cells specifying the
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| /linux/drivers/pinctrl/cirrus/ |
| H A D | pinctrl-madera-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2018 Cirrus Logic
17 #include <linux/pinctrl/pinconf-generic.h>
25 #include "../pinctrl-utils.h"
27 #include "pinctrl-madera.h"
31 * NOTE: IDs are zero-indexed for coding convenience
77 * All single-pin functions can be mapped to any GPIO, however pinmux applies
81 * Since these do not correspond to anything in the actual hardware - they are
82 * merely an adaptation to pinctrl's view of the world - we use the same name
94 /* set of pin numbers for single-pin groups, zero-indexed */
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| /linux/drivers/w1/slaves/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire slaves configuration
6 menu "1-wire Slaves"
11 Say Y here if you want to connect 1-wire thermal sensors to your
17 Say Y here if you want to connect 1-wire
23 Say Y or M here if you want to use a DS2405 1-wire
24 single-channel addressable switch.
25 This device can also work as a single-channel
29 tristate "8-Channel Addressable Switch (IO Expander) 0x29 family support (DS2408)"
31 Say Y here if you want to use a 1-wire
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | thine,thc63lvd1024.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 streams to parallel data outputs. The chip supports single/dual input/output
19 Single or dual operation mode, output data mapping and DDR output modes are
20 configured through input signals and the chip does not expose any control
30 The device can operate in single or dual input and output modes.
32 When operating in single input mode, all pixels are received on port@0,
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
30 Chip select used by the device.
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| /linux/sound/pci/echoaudio/ |
| H A D | echoaudio.h | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
34 +-----------+
35 record | |<-------------------- Inputs
36 <-------| | |
39 ------->| | +-------+
40 play | |--->|monitor|-------> Outputs
41 +-----------+ | mixer |
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| /linux/drivers/pwm/ |
| H A D | pwm-cros-ec.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/mfd/cros_ec.h>
19 * struct cros_ec_pwm_device - Driver data for EC PWM
29 static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *chip) in pwm_to_cros_ec_pwm() argument
31 return pwmchip_get_drvdata(chip); in pwm_to_cros_ec_pwm()
44 return -EINVAL; in cros_ec_dt_type_to_pwm_type()
51 struct cros_ec_device *ec = ec_pwm->ec; in cros_ec_pwm_set_duty()
62 msg->version = 0; in cros_ec_pwm_set_duty()
63 msg->command = EC_CMD_PWM_SET_DUTY; in cros_ec_pwm_set_duty()
64 msg->insize = 0; in cros_ec_pwm_set_duty()
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| /linux/drivers/net/wireless/ath/ath9k/ |
| H A D | ar9002_phy.c | 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
27 * into a single-chip and require less programming.
29 * The following single-chips exist with a respective embedded radio:
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
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