| /freebsd/sys/dev/sdio/ |
| H A D | sdiodevs | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 * --------------------------------------------------------------------------
52 * --------------------------------------------------------------------------
59 product REALTEK RTW8723BS 0xb723 802.11bgn SDIO WLAN with Bluetooth 4.0 Single-Chip Controller
62 product REALTEK RTW8822BS 0xb822 802.11ac/abgn SDIO WLAN with Bluetooth 4.1 Single-Chip Controller
63 product REALTEK RTW8821CS 0xc821 802.11ac/abgn SDIO WLAN with Bluetooth 4.2 Single-Chip Controller
64 product REALTEK RTW8822CS 0xc822 802.11ac/abgn SDIO WLAN with Bluetooth x.x Single-Chip Controller
65 product REALTEK RTW8723DS_1ANT 0xd724 802.11bgn SDIO WLAN with Bluetooth 4.2 Single-Chip Controller
66 product REALTEK RTW8723DS_2ANT 0xd723 802.11bgn SDIO WLAN with Bluetooth 4.2 Single-Chip Controller
|
| /freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | ina3221.txt | 5 - compatible: Must be "ti,ina3221"
6 - reg: I2C address
9 - ti,single-shot: This chip has two power modes: single-shot (chip takes one
11 chip takes continuous measurements). The continuous mode is
13 but the single-shot mode is more power-friendly and useful
14 for battery-powered device which cares power consumptions
16 If this property is present, the single-shot mode will be
22 - #address-cells: Required only if a child node is present. Must be 1.
23 - #size-cells: Required only if a child node is present. Must be 0.
27 - reg: Must be 0, 1 or 2, corresponding to IN1, IN2 or IN3 port of INA3221
[all …]
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| /freebsd/share/man/man4/ |
| H A D | run.4 | 1 .\"-
2 .\" SPDX-License-Identifier: ISC
30 .Bd -ragged -offset indent
41 .Bd -ragged -offset indent
48 .Bd -literal -offset indent
59 an RT2720 (1T2R) or RT2750 (dual-band 1T2R) radio transceiver.
62 an RT2820 (2T3R) or RT2850 (dual-band 2T3R) radio transceiver.
64 The RT3000U is a single-chip solution based on an RT3070 MAC/BBP and
65 an RT3020 (1T1R), RT3021 (1T2R) or RT3022 (2T2R) single-band radio
68 The RT3900E is a single-chip USB 2.0 802.11n solution.
[all …]
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| H A D | le.4 | 3 .\"-
8 .\" at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
47 .Bd -ragged -offset indent
54 .Bd -literal -offset indent
58 For ISA non-PnP adapters, the port address as well as the IRQ and the DRQ
78 .Pq CMOS, pin-compatible
91 family of chips, which are single-chip implementations of a
93 chip and a DMA engine.
99 .Tn AMD Am79C970 PCnet-PCI
101 .Tn AMD Am79C971 PCnet-FAST
[all …]
|
| H A D | rsu.4 | 1 .\"-
2 .\" SPDX-License-Identifier: ISC
29 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
44 rsu-rtl8712fw_load="YES"
53 a MAC, a 1T1R capable baseband and an RF in a single chip.
56 The RTL8191SU is a highly integrated multiple-in, single-out (MISO)
58 RF in a single chip.
61 The RTL8192SU is a highly integrated multiple-in, multiple-out (MIMO)
63 RF in a single chip.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
30 Chip select used by the device.
[all …]
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| H A D | nuvoton,npcm-fiu.txt | 3 NPCM FIU supports single, dual and quad communication interface.
6 FIU0 and FIUx supports two chip selects,
7 FIU3 support four chip select.
10 FIU0 and FIUx supports two chip selects,
11 FIU1 and FIU3 supports four chip selects.
14 - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
15 "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
16 - #address-cells : should be 1.
17 - #size-cells : should be 0.
18 - reg : the first contains the register location and length,
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | renesas,rcar-gyroadc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car GyroADC
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
15 are sampled by the GyroADC block in a round-robin fashion and the result
23 - enum:
24 - renesas,r8a7791-gyroadc
25 - renesas,r8a7792-gyroadc
[all …]
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| H A D | renesas,gyroadc.txt | 1 * Renesas R-Car GyroADC device driver
5 are sampled by the GyroADC block in a round-robin fashion and the result
9 - compatible: Should be "<soc-specific>", "renesas,rcar-gyroadc".
10 The <soc-specific> should be one of:
11 renesas,r8a7791-gyroadc - for the GyroADC block present
13 renesas,r8a7792-gyroadc - for the GyroADC with interrupt
15 - reg: Address and length of the register set for the device
16 - clocks: References to all the clocks specified in the clock-names
18 Documentation/devicetree/bindings/clock/clock-bindings.txt.
19 - clock-names: Shall contain "fck". The "fck" is the GyroADC block clock.
[all …]
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| H A D | adi,ad7944.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of pin-compatible single channel differential analog to digital
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad7944
27 - adi,ad7985
28 - adi,ad7986
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/ |
| H A D | other.json | 5 …"BriefDescription": "Number of cycles in single lpar mode. All threads in the core are assigned to…
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
36 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w…
41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a…
42 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w…
65 …ump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the origi…
66 …(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group…
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controlle
[all...] |
| H A D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mux/ |
| H A D | mux-controller.txt | 7 multiplexer needed by each consumer, but a single mux controller can of course
8 control several multiplexers for a single consumer.
11 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
12 0-7 for an 8-way multiplexer, etc.
16 ---------
19 want to use with a property containing a 'mux-ctrl-list':
21 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
22 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
23 mux-ctrl-phandle : phandle to mux controller node
24 mux-ctrl-specifier : array of #mux-control-cells specifying the
[all …]
|
| H A D | mux-consumer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
19 mux-ctrl-specifier : array of #mux-control-cells specifying the
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/fsi/ |
| H A D | fsi.txt | 4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | thine,thc63lvd1024.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 streams to parallel data outputs. The chip supports single/dual input/output
19 Single or dual operation mode, output data mapping and DDR output modes are
20 configured through input signals and the chip does not expose any control
30 The device can operate in single or dual input and output modes.
32 When operating in single input mode, all pixels are received on port@0,
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | syna.txt | 3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
43 cpu-ctrl@f7dd0000 {
44 compatible = "marvell,berlin-cpu-ctrl";
[all …]
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| H A D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-jun
[all...] |
| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/leds/ |
| H A D | leds-is31fl319x.txt | 1 LEDs connected to is31fl319x LED controller chip
4 - compatible : Should be any of
10 "si-en,sn3199".
11 - #address-cells: Must be 1.
12 - #size-cells: Must be 0.
13 - reg: 0x64, 0x65, 0x66, or 0x67.
16 - audio-gain-db : audio gain selection for external analog modulation input.
17 Valid values: 0 - 21, step by 3 (rounded down)
19 - shutdown-gpios : Specifier of the GPIO connected to SDB pin of the chip.
21 Each led is represented as a sub-node of the issi,is31fl319x device.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | ov7251.txt | 1 * Omnivision 1/7.5-Inch B&W VGA CMOS Digital Image Sensor
3 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
8 - compatible: Value should be "ovti,ov7251".
9 - clocks: Reference to the xclk clock.
10 - clock-names: Should be "xclk".
11 - clock-frequency: Frequency of the xclk clock.
12 - enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
14 - vdddo-supply: Chip digital IO regulator.
15 - vdda-supply: Chip analog regulator.
16 - vddd-supply: Chip digital core regulator.
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar9002/ |
| H A D | ar9287_attach.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
39 static const HAL_PERCAL_DATA ar9287_iq_cal = { /* single sample */
46 static const HAL_PERCAL_DATA ar9287_adc_gain_cal = { /* single sample */
53 static const HAL_PERCAL_DATA ar9287_adc_dc_cal = { /* single sample */
85 .totalSizeDesired = { -55, -55, -55, -55, -62 }, in ar9287AniSetup()
86 .coarseHigh = { -14, -14, -14, -14, -12 }, in ar9287AniSetup()
87 .coarseLow = { -64, -64, -64, -64, -70 }, in ar9287AniSetup()
88 .firpwr = { -78, -78, -78, -78, -80 }, in ar9287AniSetup()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mips/cavium/ |
| H A D | bootbus.txt | 3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
[all …]
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