Searched +full:sierra +full:- +full:phy +full:- +full:t0 (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Cadence Sierra PHY10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink14 - Swapnil Jakhade <sjakhade@cadence.com>15 - Yuti Amonkar <yamonkar@cadence.com>20 - cdns,sierra-phy-t021 - ti,sierra-phy-t0[all …]
1 Cadence Sierra PHY2 -----------------------5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.7 - resets: Must contain an entry for each in reset-names.9 - reset-names: Must include "sierra_reset" and "sierra_apb".10 "sierra_reset" must control the reset line to the PHY.11 "sierra_apb" must control the reset line to the APB PHY13 - reg: register range for the PHY.14 - #address-cells: Must be 1[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/4 ---[all...]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/phy/phy-ti.h>9 #include <dt-bindings/mux/mux.h>11 #include "k3-serdes.h"14 cmn_refclk: clock-cmnrefclk {15 #clock-cells = <0>;16 compatible = "fixed-clock";17 clock-frequency = <0>;[all …]
5 # Date: 2024-11-25 03:15:028 # the PCI ID Project at https://pci-ids.ucw.cz/.14 # (version 2 or higher) or the 3-clause BSD License.25 # device device_name <-- single tab26 # subvendor subdevice subsystem_name <-- two tabs30 # This is a relabelled RTL-813931 8139 AT-2500TX V3 Ethernet41 7a09 PCI-to-PCI Bridge50 7a19 PCI-to-PCI Bridge55 7a29 PCI-to-PCI Bridge[all …]