Searched full:sic1 (Results 1 – 3 of 3) sorted by relevance
334 u8 sic1, fmr1; in pef2256_setup_e1_system() local374 sic1 = PEF2256_SIC1_SSC_2048; in pef2256_setup_e1_system()377 sic1 = PEF2256_SIC1_SSC_4096; in pef2256_setup_e1_system()380 sic1 = PEF2256_SIC1_SSC_8192; in pef2256_setup_e1_system()383 sic1 = PEF2256_SIC1_SSC_16384; in pef2256_setup_e1_system()389 pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSC_MASK, sic1); in pef2256_setup_e1_system()395 sic1 = PEF2256_SIC1_SSD_2048; in pef2256_setup_e1_system()399 sic1 = PEF2256_SIC1_SSD_4096; in pef2256_setup_e1_system()403 sic1 = PEF2256_SIC1_SSD_8192; in pef2256_setup_e1_system()407 sic1 = PEF2256_SIC1_SSD_16384; in pef2256_setup_e1_system()[all …]
45 /* SSD is defined on 2 bits. The other bit is on SIC1 register */
45 interrupt-parent = <&sic1>;