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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/soc/rockchip,vop2.h>
15 #include <dt-bindings/usb/pd.h>
16 #include "rk3588-friendlyelec-cm3588.dtsi"
20 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
22 adc_key_recovery: adc-key-recovery {
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/linux/drivers/net/phy/
H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
129 * The value is calculated as following: (1/1000000)/((2^-32)/4)
135 * The value is calculated as following: (1/1000000)/((2^-32)/8)
189 #define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8) argument
332 #define LAN8814_GPIO_EN_ADDR(pin) \ argument
333 ((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)
334 #define LAN8814_GPIO_EN_BIT(pin) BIT(pin) argument
335 #define LAN8814_GPIO_DIR_ADDR(pin) \ argument
336 ((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)
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/linux/tools/testing/selftests/mm/
H A Dgup_longterm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GUP long-term page pinning tests.
54 * R/W long-term pinning. For these filesystems, we can be fairly sure in fs_is_unknown()
91 static void do_test(int fd, size_t size, enum test_type type, bool shared) in do_test() argument
136 shared ? MAP_SHARED : MAP_PRIVATE, fd, 0); in do_test()
138 if (size == pagesize || shared) { in do_test()
148 /* Fault in the page such that GUP-fast can pin it directly. */ in do_test()
156 * long-term R/O pinning by mapping the page R/O. in do_test()
179 if (rw && shared && fs_is_unknown(fs_type)) { in do_test()
186 * expected to work. Otherwise, we expect long-term R/W pinning in do_test()
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H A Dcow.c1 // SPDX-License-Identifier: GPL-2.0-only
72 for (; size; addr += pagesize, size -= pagesize) in range_is_swapped()
85 if (pipe(comm_pipes->child_ready) < 0) { in setup_comm_pipes()
87 return -errno; in setup_comm_pipes()
89 if (pipe(comm_pipes->parent_ready) < 0) { in setup_comm_pipes()
91 close(comm_pipes->child_ready[0]); in setup_comm_pipes()
92 close(comm_pipes->child_ready[1]); in setup_comm_pipes()
93 return -errno; in setup_comm_pipes()
101 close(comm_pipes->child_ready[0]); in close_comm_pipes()
102 close(comm_pipes->child_ready[1]); in close_comm_pipes()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dclock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
37 #include <rdma/mlx5-abi.h>
78 MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN = -200000,
103 if (!clock->shared) in mlx5_clock_lockdep_assert()
106 lockdep_assert(lockdep_is_held(&clock_priv(clock)->lock)); in mlx5_clock_lockdep_assert()
113 return clock_priv(clock)->mdev; in mlx5_clock_mdev_get()
118 if (!clock->shared) in mlx5_clock_lock()
121 mutex_lock(&clock_priv(clock)->lock); in mlx5_clock_lock()
126 if (!clock->shared) in mlx5_clock_unlock()
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/linux/sound/hda/codecs/
H A Dgeneric.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Generic BIOS auto-parser helper functions for HD-audio
16 /* table entry for multi-io paths */
18 hda_nid_t pin; /* multi-io widget pin NID */ member
20 unsigned int ctl_in; /* cached input-pin control value */
25 * For output, stored in the order of DAC -> ... -> pin,
26 * for input, pin -> ... -> ADC.
30 * multi[] indicates whether it's a selector widget with multi-connectors
52 bool pin_fixed:1; /* path with fixed pin */
56 /* mic/line-in auto switching entry */
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/linux/Documentation/devicetree/bindings/sound/
H A Dmediatek,mt8188-afe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8188-afe
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See dtschema reserved-memory/shared-dma-pool.yaml for details.
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H A Dmt8195-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8195-audio
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See ../reserved-memory/reserved-memory.txt for details.
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/linux/Documentation/driver-api/gpio/
H A Dintro.rst17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
23 passes such pin configuration data to drivers.
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
29 often have a few such pins to help with pin scarcity on SOCs; and there are
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Drenesas,rcar-gyroadc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car GyroADC
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
15 are sampled by the GyroADC block in a round-robin fashion and the result
23 - enum:
24 - renesas,r8a7791-gyroadc
25 - renesas,r8a7792-gyroadc
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/linux/drivers/staging/iio/Documentation/
H A Dsysfs-bus-iio-dds4 Contact: linux-iio@vger.kernel.org
8 which allows for pin controlled FSK Frequency Shift Keying
15 Contact: linux-iio@vger.kernel.org
18 obtain the desired value in Hz. If shared across all frequency
20 if shared across all channels.
24 Contact: linux-iio@vger.kernel.org
34 Contact: linux-iio@vger.kernel.org
38 allows for pin controlled PSK Phase Shift Keying
45 Contact: linux-iio@vger.kernel.org
48 the desired value in rad. If shared across all phase registers
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
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H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_dma_buf.c42 #include <linux/dma-buf.h>
43 #include <linux/dma-fence-array.h>
44 #include <linux/pci-p2pdma.h>
49 * dma_buf_attach_adev - Helper to get adev of an attachment
59 if (attach->importer_ops == &amdgpu_dma_buf_attach_ops) { in dma_buf_attach_adev()
60 struct drm_gem_object *obj = attach->importer_priv; in dma_buf_attach_adev()
63 return amdgpu_ttm_adev(bo->tbo.bdev); in dma_buf_attach_adev()
70 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
72 * @dmabuf: DMA-buf where we attach to
75 * Add the attachment as user to the exported DMA-buf.
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/linux/rust/kernel/sync/
H A Darc.rs1 // SPDX-License-Identifier: GPL-2.0
3 //! A reference-counted pointer.
5 //! This module implements a way for users to create reference-counted objects and pointers to
17 //! [`Arc`]: https://doc.rust-lang.org/std/sync/struct.Arc.html
34 pin::Pin,
41 /// A reference-counted pointer to an instance of `T`.
48 /// The reference count on an instance of [`Arc`] is always non-zer
823 impl<T: ?Sized> From<UniqueArc<T>> for Pin<UniqueArc<T>> { global() implementation
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/linux/arch/arm/mach-orion5x/
H A Dboard-mss2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Maxtor Shared Storage II Board Setup
13 #include <asm/mach-types.h>
17 #include "bridge-regs.h"
21 * Maxtor Shared Storage II Info
27 static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in mss2_pci_map_irq() argument
32 * Check for devices with hard-wired IRQs. in mss2_pci_map_irq()
34 irq = orion5x_pci_map_irq(dev, slot, pin); in mss2_pci_map_irq()
35 if (irq != -1) in mss2_pci_map_irq()
38 return -1; in mss2_pci_map_irq()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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H A Dintel,pinctrl-keembay.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay pin controller
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
13 Intel Keem Bay SoC integrates a pin controller which enables control
14 of pin directions, input/output values and configuration
19 const: intel,keembay-pinctrl
24 gpio-controller: true
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H A Dpinctrl-st.txt1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
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/linux/Documentation/devicetree/bindings/input/
H A Dnvidia,tegra20-kbc.txt2 The key controller has maximum 24 pins to make matrix keypad. Any pin
3 can be configured as row or column. The maximum column pin can be 8
7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
11 array of pin numbers which is used as rows.
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
13 array of pin numbers which is used as column.
14 - linux,keymap: The keymap for keys as described in the binding document
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/linux/arch/arm/boot/dts/st/
H A Dste-href-tvk1281618-r2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-keys";
12 #address-cells = <1>;
13 #size-cells = <0>;
14 vdd-supply = <&ab8500_ldo_aux1_reg>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
37 interrupt-parent = <&gpio6>;
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/linux/arch/mips/pci/
H A Dfixup-ip32.c1 // SPDX-License-Identifier: GPL-2.0
27 {0, 0, 0, 0, 0}, /* This is placeholder row - never used */
37 * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
38 * the device (1-4 => A-D), tell what irq to use. Note that we don't
39 * in theory have slots 4 and 5, and we never normally use the shared
40 * irqs. I suppose a device without a pin A will thank us for doing it
43 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in pcibios_map_irq() argument
45 return irq_tab_mace[slot][pin]; in pcibios_map_irq()
/linux/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1000.h12 #include <asm/mach-au1x00/au1000.h>
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
47 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); in au1000_gpio1_to_irq()
52 return -ENXIO; in au1000_gpio2_to_irq()
58 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0; in au1000_irq_to_gpio()
60 return -ENXIO; in au1000_irq_to_gpio()
65 gpio -= ALCHEMY_GPIO1_BASE; in au1500_gpio1_to_irq()
73 return -ENXIO; in au1500_gpio1_to_irq()
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/linux/arch/x86/platform/geode/
H A Dgeode-common.h1 // SPDX-License-Identifier: GPL-2.0-only
3 * Shared helpers to register GPIO-connected buttons and LEDs
13 unsigned int pin; member
17 int geode_create_restart_key(unsigned int pin);
/linux/Documentation/spi/
H A Dspi-lm70llp.rst2 spi_lm70llp : LM70-LLP parport-to-SPI adapter
15 -----------
27 --------------------
28 The schematic for this particular board (the LM70EVAL-LLP) is
39 D0 2 - -
40 D1 3 --> V+ 5
41 D2 4 --> V+ 5
42 D3 5 --> V+ 5
43 D4 6 --> V+ 5
44 D5 7 --> nCS 8
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