| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_top.h | 15 * struct traffic_shaper_cfg: traffic shaper configuration
16 * @en : enable/disable traffic shaper
82 * @setup_traffic_shaper : programs traffic shaper control
94 * setup_traffic_shaper() : Setup traffic shaper control
96 * @cfg : traffic shaper configuration
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| /linux/include/linux/platform_data/ |
| H A D | lp855x.h | 109 LP8556_COMBINED1, /* pwm + i2c before the shaper block */
111 LP8556_COMBINED2, /* pwm + i2c after the shaper block */
117 LP8557_COMBINED1, /* pwm + i2c after the shaper block */
118 LP8557_COMBINED2, /* pwm + i2c before the shaper block */
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| /linux/net/sched/ |
| H A D | sch_mqprio.c | 26 u16 shaper; member
48 if (priv->shaper != TC_MQPRIO_SHAPER_DCB) in mqprio_enable_offload()
56 mqprio.shaper = priv->shaper; in mqprio_enable_offload()
274 priv->shaper = nla_get_u16(tb[TCA_MQPRIO_SHAPER]); in mqprio_parse_nlattr()
278 if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) { in mqprio_parse_nlattr()
280 "min_rate accepted only when shaper is in bw_rlimit mode"); in mqprio_parse_nlattr()
307 if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) { in mqprio_parse_nlattr()
309 "max_rate accepted only when shaper is in bw_rlimit mode"); in mqprio_parse_nlattr()
595 nla_put_u16(skb, TCA_MQPRIO_SHAPER, priv->shaper)) in mqprio_dump()
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| H A D | sch_cake.c | 18 * - An overall bandwidth shaper, to move the bottleneck away from dumb CPE
44 * a bandwidth tracker which reuses the shaper logic to detect which side of the
1523 * and to the global shaper. in cake_advance_shaper()
1763 /* ensure shaper state isn't stale */ in cake_enqueue()
1990 /* global hard shaper */ in cake_dequeue()
2003 /* In unlimited mode, can't rely on shaper timings, just balance in cake_dequeue()
3137 MODULE_DESCRIPTION("The CAKE shaper.");
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| /linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| H A D | hclge_tm.h | 201 u8 ir_b; /* IR_B parameter of IR shaper */
202 u8 ir_u; /* IR_U parameter of IR shaper */
203 u8 ir_s; /* IR_S parameter of IR shaper */
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| H A D | hclge_tm.c | 26 /* hclge_shaper_para_calc: calculate ir parameter for the shaper
28 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
29 * @ir_para: parameters of IR shaper
899 /* Calc shaper para */ in hclge_tm_pg_shaper_cfg()
1150 /* Need config vport shaper */ in hclge_tm_pri_vnet_base_shaper_cfg()
1477 /* Cfg tm shaper */ in hclge_tm_schd_setup_hw()
1848 "failed to get qset %u shaper, ret = %d\n", qset_id, in hclge_tm_get_qset_shaper()
1923 "failed to get priority shaper(%#x), ret = %d\n", in hclge_tm_get_pri_shaper()
2077 "failed to get pg shaper(%#x), ret = %d\n", in hclge_tm_get_pg_shaper()
2105 "failed to get port shaper, ret = %d\n", ret); in hclge_tm_get_port_shaper()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.h | 88 struct dc_transfer_func **shaper);
94 struct dc_transfer_func **shaper);
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| H A D | dcn30_resource.c | 1433 struct dc_transfer_func **shaper) in dcn30_acquire_post_bldn_3dlut() argument
1439 ASSERT(*lut == NULL && *shaper == NULL); in dcn30_acquire_post_bldn_3dlut()
1441 *shaper = NULL; in dcn30_acquire_post_bldn_3dlut()
1446 *shaper = pool->mpc_shaper[i]; in dcn30_acquire_post_bldn_3dlut()
1468 struct dc_transfer_func **shaper) in dcn30_release_post_bldn_3dlut() argument
1474 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { in dcn30_release_post_bldn_3dlut()
1478 *shaper = NULL; in dcn30_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_color.c | 108 * degamma TF, shaper TF (before 3D LUT), and blend(dpp.ogam) TF and
761 * If user shaper LUT is set, we assume a linear color space in amdgpu_dm_atomic_shaper_lut()
808 * shaper and 3D LUTs match the hw supported size
813 * newer) and if the user shaper and 3D LUTs match the supported size.
822 const struct drm_color_lut *shaper = NULL, *lut3d = NULL; in amdgpu_dm_verify_lut3d_size() local
826 /* shaper LUT is only available if 3D LUT color caps */ in amdgpu_dm_verify_lut3d_size()
828 shaper = __extract_blob_lut(dm_plane_state->shaper_lut, &size); in amdgpu_dm_verify_lut3d_size()
830 if (shaper && size != exp_size) { in amdgpu_dm_verify_lut3d_size()
832 "Invalid Shaper LUT size. Should be %u but got %u.\n", in amdgpu_dm_verify_lut3d_size()
1166 "setting plane %d shaper LUT failed.\n", in amdgpu_dm_plane_set_color_properties()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_mode.h | 369 * @shaper_lut_property: Plane property to set pre-blending shaper LUT
378 * pre-blending shaper LUT as supported by the driver (read-only).
383 * transfer function for pre-blending shaper (before applying 3D LUT)
384 * with or without LUT. There is no shaper ROM, but we can use AMD
410 * conversion. It works as a post-3DLUT 1D LUT. With shaper LUT, they
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| /linux/drivers/net/ethernet/mscc/ |
| H A D | ocelot_police.h | 14 MSCC_QOS_RATE_MODE_DISABLED, /* Policer/shaper disabled */
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| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | iavf.rst | 156 The shaper bw_rlimit parameter is optional.
164 queues 16@0 16@16 hw 1 mode channel shaper bw_rlimit min_rate 1Gbit 2Gbit
178 shaper bw_rlimit: for each tc, sets minimum and maximum bandwidth rates.
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| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | hirschmann,hellcreek.yaml | 21 Shaper.
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
| H A D | dcn35_dpp.c | 114 ….dpp_program_shaper_lut = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, prog…
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 194 struct dc_transfer_func **shaper);
200 struct dc_transfer_func **shaper);
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| /linux/drivers/net/ethernet/ti/ |
| H A D | Kconfig | 142 Time Aware Shaper (TAS) / Enhanced Scheduled Traffic (EST),
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| /linux/include/uapi/linux/ |
| H A D | dcbnl.h | 38 * @cbs: credit based shaper ets algorithm supported
53 * 1 credit-based shaper
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| /linux/include/net/ |
| H A D | pkt_sched.h | 175 u16 shaper; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1599 struct dc_transfer_func **shaper) in dcn32_acquire_post_bldn_3dlut() argument
1603 ASSERT(*lut == NULL && *shaper == NULL); in dcn32_acquire_post_bldn_3dlut()
1605 *shaper = NULL; in dcn32_acquire_post_bldn_3dlut()
1609 *shaper = pool->mpc_shaper[mpcc_id]; in dcn32_acquire_post_bldn_3dlut()
1620 struct dc_transfer_func **shaper) in dcn32_release_post_bldn_3dlut() argument
1626 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { in dcn32_release_post_bldn_3dlut()
1630 *shaper = NULL; in dcn32_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 79 DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode" in dcn30_log_color_state()
163 " SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT" in dcn30_log_color_state()
255 //get the shaper lut params in dcn30_set_mpc_shaper_3dlut()
391 /*program rmu shaper and 3dlut in MPC*/ in dcn30_set_output_transfer_func()
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| /linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_tc_mqprio.c | 28 } else if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) { in cxgb4_mqprio_validate()
29 netdev_err(dev, "Only bandwidth rate shaper supported\n"); in cxgb4_mqprio_validate()
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| /linux/drivers/atm/ |
| H A D | midway.h | 17 #define TS_CLOCK 25000000 /* traffic shaper clock (cell/sec) */
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| /linux/drivers/net/ethernet/intel/iavf/ |
| H A D | iavf_main.c | 2972 * After a reset, the shaper parameters of queues need to be replayed again.
4986 const struct net_shaper *shaper, in iavf_verify_shaper() argument
4992 if (shaper->handle.scope == NET_SHAPER_SCOPE_QUEUE) { in iavf_verify_shaper()
4993 vf_max = adapter->qos_caps->cap[0].shaper.peak; in iavf_verify_shaper()
4994 if (vf_max && shaper->bw_max > vf_max) { in iavf_verify_shaper()
4996 shaper->bw_max, shaper->handle.id, in iavf_verify_shaper()
5006 const struct net_shaper *shaper, in iavf_shaper_set() argument
5010 const struct net_shaper_handle *handle = &shaper->handle; in iavf_shaper_set()
5018 ret = iavf_verify_shaper(binding, shaper, extack); in iavf_shaper_set()
5024 tx_ring->q_shaper.bw_min = div_u64(shaper->bw_min, 1000); in iavf_shaper_set()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 444 /* Shaper */ in dcn401_populate_mcm_luts()
445 if (mcm_luts.shaper) { in dcn401_populate_mcm_luts()
447 if (mcm_luts.shaper->type == TF_TYPE_HWPWL) in dcn401_populate_mcm_luts()
448 m_lut_params.pwl = &mcm_luts.shaper->pwl; in dcn401_populate_mcm_luts()
449 else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { in dcn401_populate_mcm_luts()
452 mcm_luts.shaper, in dcn401_populate_mcm_luts()
613 // Shaper in dcn401_set_mcm_luts()
646 /*program shaper and 3dlut in MPC*/ in dcn401_set_output_transfer_func()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/ |
| H A D | dcn32_dpp.c | 126 ….dpp_program_shaper_lut = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, prog…
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