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Searched +full:serdes +full:- +full:dfe +full:- +full:tap +full:- +full:enable (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/net/
H A Damd-xgbe.txt1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
13 amd,per-channel-interrupt property is specified, then one additional
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_interface.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
38 * SerDes HAL driver API
39 * @ingroup group_serdes SerDes
44 * @brief Header file for the SerDes HAL driver
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
65 /* Relevant to Serdes hssp and 25g */
68 /* Relevant to Serdes hssp only */
71 /* Relevant to Serdes hssp and 25g */
73 /* Relevant to Serdes hssp only */
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/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-xgbe-b.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "amd,xgbe-seattle-v1a";
12 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
13 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
14 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
18 amd,per-channel-interrupt;
19 amd,speed-set = <0>;
20 amd,serdes-blwc = <1>, <1>, <0>;
21 amd,serdes-cdr-rate = <2>, <2>, <7>;
22 amd,serdes-pq-skew = <10>, <10>, <18>;
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/freebsd/sys/dev/axgbe/
H A Dxgbe.h4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
134 #define XGBE_DRV_NAME "amd-xgbe"
151 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
157 * - Maximum number of SKB frags
158 * - Maximum descriptors for contiguous TSO/GSO packet
159 * - Possible context descriptor
160 * - Possible TSO header descriptor
174 /* DMA cache settings - Outer sharable, write-back, write-allocat
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/freebsd/sys/dev/al_eth/
H A Dal_init_eth_lm.c1 /*-
43 /* delay before checking link status with new serdes parameters (uSec) */
51 /* num of link training failures till serdes reset */
73 /* 40GBASE-LR4 and 40GBASE-SR4 are optic modules */
185 /* Enable loop filter auto-adjust */
189 /* Disable the DFE since most applications do not need it (6.18) */
193 /* Enable FIR (6.12) */
195 /* Set Main-cursor tap sign to positive (6.12) */
197 /* Set Post-cursor tap sign to negative (6.12) */
199 /* Set Pre-cursor tap sign to negative (6.12) */
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
73 … 0x003818UL //Access:RW DataWidth:0x6 // Statistic mask enable Bit5 : Mask Messa…
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
98 … (0x1<<0) // I/O space access enable. There are no I/O…
100 … (0x1<<1) // Memory space access enable.
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs_mcdi.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
32 /* Power-on reset state */
54 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
57 /* The rest of these are firmware-defined */
65 /* Values to be written to the per-port status dword in shared
94 * | | \--- Response
95 * | \------- Error
96 * \------------------------------ Resync (always set)
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