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Searched +full:serdes +full:- +full:cdr +full:- +full:rate (Results 1 – 5 of 5) sorted by relevance

/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-xgbe-b.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "amd,xgbe-seattle-v1a";
12 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
13 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
14 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
18 amd,per-channel-interrupt;
19 amd,speed-set = <0>;
20 amd,serdes-blwc = <1>, <1>, <0>;
21 amd,serdes-cdr-rate = <2>, <2>, <7>;
22 amd,serdes-pq-skew = <10>, <10>, <18>;
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/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
31 #define PHY_A(serdes) 0 argument
184 /* Set Lane Control Rate */ in netcp_xgbe_serdes_lane_enable()
219 ret = -ETIMEDOUT; in netcp_xgbe_wait_pll_locked()
226 pr_err("XGBE serdes not locked: time out.\n"); in netcp_xgbe_wait_pll_locked()
258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
301 pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n", in netcp_xgbe_serdes_reset_cdr()
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
47 /* LED Blink rate that will achieve ~15.9Hz */
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
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