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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmvebu-sdram-controller.txt1 Device Tree bindings for MVEBU SDRAM controllers
3 The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
8 Armada XP SDRAM controller.
12 - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
14 include all SDRAM controller registers as per the datasheet.
19 compatible = "marvell,armada-xp-sdram-controller";
H A Dmarvell,mvebu-sdram-controller.yaml4 $id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
7 title: Marvell MVEBU SDRAM controller
15 const: marvell,armada-xp-sdram-controller
29 compatible = "marvell,armada-xp-sdram-controller";
H A Dnvidia,tegra20-emc.yaml15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
/freebsd/sys/contrib/device-tree/Bindings/arm/altera/
H A Dsocfpga-sdram-edac.txt1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
5 - compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
7 - interrupts : Should contain the SDRAM ECC IRQ in the
12 compatible = "altr,sdram-edac";
H A Dsocfpga-sdram-controller.txt1 Altera SOCFPGA SDRAM Controller
5 syscon is required by the Altera SOCFPGA SDRAM EDAC.
/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Daspeed-sdram-edac.txt15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
24 edac: sdram@1e6e0000 {
25 compatible = "aspeed,ast2500-sdram-edac";
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_vcbus.c49 * interfaces. Currently, we only deal with peripheral/SDRAM address spaces
52 * The SDRAM address space is consistently mapped starting at 0 and extends to
53 * the size of the installed SDRAM.
65 /* SDRAM */
81 /* SDRAM */
97 /* SDRAM */
112 * The BCM2838 supports up to 4GB of SDRAM, but unfortunately we can still only
114 * peripherals can still only access the lower end of SDRAM. For this reason,
119 /* SDRAM */
H A Dbcm2835_vcbus.h56 * Max allowed SDRAM mapping for most peripherals. The Raspberry Pi 4 has more
57 * than 1 GB of SDRAM, but only the lowest 1 GB is mapped into the "Legacy
H A Dbcm2835_cpufreq.c1102 "current ARM %dMHz, Core %dMHz, SDRAM %dMHz, Turbo %s\n", in bcm2835_cpufreq_init()
1107 "max/min ARM %d/%dMHz, Core %d/%dMHz, SDRAM %d/%dMHz\n", in bcm2835_cpufreq_init()
1136 "ARM %dMHz, Core %dMHz, SDRAM %dMHz, Turbo %s\n", in bcm2835_cpufreq_init()
1273 "SDRAM frequency (Hz)"); in bcm2835_cpufreq_attach()
1293 "SDRAM voltage (offset from 1.2V in units of 0.025V)"); in bcm2835_cpufreq_attach()
1295 /* Voltage individual SDRAM */ in bcm2835_cpufreq_attach()
1300 "SDRAM controller voltage" in bcm2835_cpufreq_attach()
1306 "SDRAM I/O voltage (offset from 1.2V in units of 0.025V)"); in bcm2835_cpufreq_attach()
1311 "SDRAM phy voltage (offset from 1.2V in units of 0.025V)"); in bcm2835_cpufreq_attach()
1393 * clock down core and sdram to default first. in bcm2835_cpufreq_set()
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dralink,rt2880-pinctrl.yaml38 enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
57 enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
107 const: sdram
111 enum: [sdram]
H A Dralink,rt305x-pinctrl.yaml39 pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf,
59 enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite]
154 const: sdram
158 enum: [sdram]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ti/
H A Demif.txt1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
57 has capability for generating SDRAM temperature alerts
/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A Ddmm.txt4 SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
5 accesses such as priority generation amongst initiators, configuration of SDRAM
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr-props.yaml48 Density in megabits of SDRAM chip. Decoded from Mode Register 8.
68 IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
H A Djedec,lpddr2.yaml7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
37 Revision 1 value of SDRAM chip. Obtained from device datasheet.
45 Revision 2 value of SDRAM chip. Obtained from device datasheet.
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dsbc8548.dts24 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
25 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
H A Dsbc8548-altflash.dts27 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
28 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
H A Dwarp.dts89 SDRAM0: sdram {
90 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
H A Dsam440ep.dts96 SDRAM0: sdram {
97 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
H A Dbamboo.dts95 SDRAM0: sdram {
96 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr7s9210-rza2mevb.dts8 * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has
22 * SW6 SW6-1 set to SDRAM
79 reg = <0x0c000000 0x04000000>; /* SDRAM */
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-core-clock.txt30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dsbc8641d.dts29 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
30 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Daltera-fpga2sdram-bridge.txt1 Altera FPGA To SDRAM Bridge Driver
/freebsd/sys/i386/include/
H A Delan_mmcr.h47 /* SDRAM Controller */
61 /* SDRAM Buffer */

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