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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-sdmmc.dtsi3 * Google Veyron (and derivatives) fragment for sdmmc cards
10 mmc1 = &sdmmc;
19 sdmmc {
21 * We run sdmmc at max speed; bump up drive strength.
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
80 &sdmmc {
H A Drk3288-veyron-mighty.dts20 &sdmmc {
29 sdmmc {
30 sdmmc_wp_pin: sdmmc-wp-pin {
H A Drk3066a-bqcurie2.dts39 regulator-name = "sdmmc-supply";
168 &mmc0 { /* sdmmc */
H A Drv1108.dtsi485 sdmmc: mmc@30130000 { label
848 sdmmc {
849 sdmmc_clk: sdmmc-clk {
853 sdmmc_cmd: sdmmc-cmd {
857 sdmmc_cd: sdmmc-cd {
861 sdmmc_bus1: sdmmc-bus1 {
865 sdmmc_bus4: sdmmc-bus4 {
H A Drk3066a-marsboard.dts45 vcc_sd0: regulator-sdmmc {
47 regulator-name = "sdmmc-supply";
H A Drk3128.dtsi467 sdmmc: mmc@10214000 { label
1210 sdmmc {
1211 sdmmc_clk: sdmmc-clk {
1215 sdmmc_cmd: sdmmc-cmd {
1219 sdmmc_det: sdmmc-det {
1223 sdmmc_wp: sdmmc-wp {
1227 sdmmc_pwren: sdmmc-pwren {
1231 sdmmc_bus4: sdmmc-bus4 {
/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c162 [FUNC_SDMMC] = "sdmmc",
244 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
245 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
246 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
247 LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
249 LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
250 LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
251 LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
252 LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
253 LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc.yaml46 - description: register offset that controls the SDMMC clock phase
50 that contains the SDMMC clock-phase control register. The first value is
52 SDMMC clock phase register, and the 3rd value is the bit shift for the
H A Dwm,wm8505-sdhc.yaml37 - description: SDMMC controller interrupt
38 - description: SDMMC controller DMA interrupt
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3576-luckfox-omni3576.dts16 mmc1 = &sdmmc;
41 &sdmmc {
H A Dpx30-cobra-ltk500hd1829.dts14 mmc1 = &sdmmc;
62 &sdmmc {
H A Drk3399-rock-4c-plus.dts19 mmc1 = &sdmmc;
500 sdmmc-supply = <&vcc_sdio_s0>;
549 sdmmc {
550 sdmmc_bus4: sdmmc-bus4 {
557 sdmmc_clk: sdmmc-clk {
561 sdmmc_cmd: sdmmc-cmd {
634 &sdmmc {
H A Drk3328-evb.dts15 mmc0 = &sdmmc;
47 vcc_sd: regulator-sdmmc {
247 &sdmmc {
H A Dpx30-engicam-common.dtsi11 mmc1 = &sdmmc;
94 &sdmmc {
H A Drk3328-orangepi-r1-plus.dtsi17 mmc0 = &sdmmc;
56 vcc_sd: regulator-sdmmc {
290 &sdmmc {
H A Drk3318-a95x-z2.dts13 mmc0 = &sdmmc;
108 vcc_sd: regulator-sdmmc {
306 &sdmmc {
H A Dpx30-firefly-jd4-core-mb.dts18 mmc0 = &sdmmc;
127 &sdmmc {
H A Drk3399-evb-ind.dts15 mmc1 = &sdmmc;
352 sdmmc-supply = <&vccio_sd>;
388 &sdmmc {
H A Dpx30-ringneck-haikou.dts17 mmc2 = &sdmmc;
212 &sdmmc {
H A Drk3328-rock-pi-e.dts26 mmc0 = &sdmmc;
67 vcc_sd: regulator-sdmmc {
404 &sdmmc {
H A Drk3308-sakurapi-rk3308b.dts19 mmc1 = &sdmmc;
209 &sdmmc {
H A Drk3528-pinctrl.dtsi953 sdmmc {
955 sdmmc_bus4: sdmmc-bus4 {
968 sdmmc_clk: sdmmc-clk {
975 sdmmc_cmd: sdmmc-cmd {
982 sdmmc_det: sdmmc-det {
989 sdmmc_pwren: sdmmc-pwren {
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk_sdmmc.dts20 compatible = "altr,socfpga-sdmmc-ecc";
/linux/include/dt-bindings/memory/
H A Dtegra186-mc.h163 /* sdmmc memory read client */
171 /* sdmmc memory write client */
/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c372 /* Only a reset could power-off sdmmc */ in mmci_sdmmc_set_pwrreg()
378 * Set the SDMMC in Power-cycle state. in mmci_sdmmc_set_pwrreg()
398 * After a power-cycle state, we must set the SDMMC in in mmci_sdmmc_set_pwrreg()
400 * driven high. Then we can set the SDMMC to Power-on state in mmci_sdmmc_set_pwrreg()

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