| /freebsd/sys/contrib/device-tree/src/arm/rockchip/ |
| H A D | rk3288-veyron-sdmmc.dtsi | 3 * Google Veyron (and derivatives) fragment for sdmmc cards
10 mmc1 = &sdmmc;
19 sdmmc {
21 * We run sdmmc at max speed; bump up drive strength.
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
80 &sdmmc {
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| H A D | rk3288-phycore-rdk.dts | 175 sdmmc {
180 sdmmc_bus4: sdmmc-bus4 {
187 sdmmc_clk: sdmmc-clk {
191 sdmmc_cmd: sdmmc-cmd {
195 sdmmc_pwr: sdmmc-pwr {
223 &sdmmc {
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| H A D | rk3288-veyron-mighty.dts | 20 &sdmmc {
29 sdmmc {
30 sdmmc_wp_pin: sdmmc-wp-pin {
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| H A D | rk3288-evb.dtsi | 170 vcc_sd: sdmmc-regulator {
224 &sdmmc {
339 sdmmc {
344 sdmmc_bus4: sdmmc-bus4 {
351 sdmmc_clk: sdmmc-clk {
355 sdmmc_cmd: sdmmc-cmd {
359 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3288-firefly-reload.dts | 110 vcc_sd: sdmmc-regulator {
241 &sdmmc {
346 sdmmc {
351 sdmmc_bus4: sdmmc-bus4 {
358 sdmmc_clk: sdmmc-clk {
362 sdmmc_cmd: sdmmc-cmd {
366 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3288-miqi.dts | 61 vcc_sd: sdmmc-regulator {
341 sdmmc {
346 sdmmc_bus4: sdmmc-bus4 {
353 sdmmc_clk: sdmmc-clk {
357 sdmmc_cmd: sdmmc-cmd {
361 sdmmc_pwr: sdmmc-pwr {
378 &sdmmc {
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| H A D | rk3288-tinker.dtsi | 97 vcc_sd: sdmmc-regulator {
407 sdmmc {
408 sdmmc_bus4: sdmmc-bus4 {
415 sdmmc_clk: sdmmc-clk {
419 sdmmc_cmd: sdmmc-cmd {
423 sdmmc_pwr: sdmmc-pwr {
455 &sdmmc {
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| H A D | rk3288-veyron-pinky.dts | 107 sdmmc {
108 sdmmc_wp_pin: sdmmc-wp-pin {
127 &sdmmc {
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| H A D | rk3288-firefly.dtsi | 91 vcc_sd: sdmmc-regulator {
440 sdmmc {
445 sdmmc_bus4: sdmmc-bus4 {
452 sdmmc_clk: sdmmc-clk {
456 sdmmc_cmd: sdmmc-cmd {
460 sdmmc_pwr: sdmmc-pwr {
498 &sdmmc {
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| H A D | rk3288-rock2-square.dts | 120 vcc_sd: sdmmc-regulator {
145 &sdmmc {
244 sdmmc {
245 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3288-vmarc-som.dtsi | 292 sdmmc {
293 sdmmc_bus4: sdmmc-bus4 {
301 sdmmc_clk: sdmmc-clk {
305 sdmmc_cmd: sdmmc-cmd {
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| H A D | rk3066a-mk808.dts | 106 vcc_sd: sdmmc-regulator {
201 sdmmc {
202 sdmmc_pwr: sdmmc-pwr {
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| H A D | rk3036.dtsi | 27 mshc1 = &sdmmc;
249 sdmmc: mmc@10214000 {
659 sdmmc {
660 sdmmc_clk: sdmmc-clk {
664 sdmmc_cmd: sdmmc-cmd {
668 sdmmc_cd: sdmmc-cd {
672 sdmmc_bus1: sdmmc-bus1 {
676 sdmmc_bus4: sdmmc-bus4 {
246 sdmmc: mmc@10214000 { global() label
|
| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | nvidia,tegra20-sdhci.yaml | 228 - const: sdmmc-3v3
230 - const: sdmmc-1v8
232 - const: sdmmc-3v3-drv
234 - const: sdmmc-1v8-drv
237 - const: sdmmc-3v3-drv
239 - const: sdmmc-1v8-drv
242 - const: sdmmc-1v8-drv
257 - const: sdmmc-3v3
259 - const: sdmmc-1v8
296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
[all …]
|
| H A D | nvidia,tegra20-sdhci.txt | 52 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
56 - pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
116 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
135 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
| H A D | synopsys-dw-mshc.yaml | 46 - description: register offset that controls the SDMMC clock phase
50 that contains the SDMMC clock-phase control register. The first value is
52 SDMMC clock phase register, and the 3rd value is the bit shift for the
|
| H A D | mmci.txt | 19 Should be defined for sdmmc variant.
30 specific for sdmmc variant:
|
| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3368-orion-r68-meta.dts | 16 mmc0 = &sdmmc;
273 sdmmc {
274 sdmmc_clk: sdmmc-clk {
278 sdmmc_cmd: sdmmc-cmd {
282 sdmmc_cd: sdmmc-cd {
286 sdmmc_bus1: sdmmc-bus1 {
290 sdmmc_bus4: sdmmc-bus4 {
310 &sdmmc {
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| H A D | rk3368-lion-haikou.dts | 14 mmc1 = &sdmmc;
71 &sdmmc {
131 sdmmc {
132 sdmmc_cd_pin: sdmmc-cd-pin {
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| H A D | rk3399-gru.dtsi | 14 mmc0 = &sdmmc;
474 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
537 &sdmmc {
546 * configured as SDMMC and not JTAG.
773 sdmmc {
775 * We run sdmmc at max speed; bump up drive strength.
778 sdmmc_bus4: sdmmc-bus4 {
786 sdmmc_clk: sdmmc-clk {
791 sdmmc_cmd: sdmmc-cmd {
805 sdmmc_cd: sdmmc
[all...] |
| H A D | rk3399-rock960.dtsi | 15 mmc1 = &sdmmc;
392 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
431 sdmmc {
432 sdmmc_bus1: sdmmc-bus1 {
437 sdmmc_bus4: sdmmc-bus4 {
445 sdmmc_clk: sdmmc-clk {
450 sdmmc_cmd: sdmmc-cmd {
549 &sdmmc {
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| H A D | rk3399-rock-4c-plus.dts | 20 mmc1 = &sdmmc;
456 sdmmc-supply = <&vcc_sdio_s0>;
499 sdmmc {
500 sdmmc_bus4: sdmmc-bus4 {
507 sdmmc_clk: sdmmc-clk {
511 sdmmc_cmd: sdmmc-cmd {
583 &sdmmc {
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| H A D | rk3308-roc-cc.dts | 14 mmc0 = &sdmmc;
81 vcc_sdmmc: vcc-sdmmc {
176 &sdmmc {
|
| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 125 SDMMC FIFO ECC
127 - compatible : Should be "altr,socfpga-sdmmc-ecc"
224 sdmmc-ecc@ff8c2c00 {
225 compatible = "altr,socfpga-sdmmc-ecc";
296 SDMMC FIFO ECC
298 - compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
376 sdmmc-ecc@ff8c8c00 {
377 compatible = "altr,socfpga-s10-sdmmc-ecc";
|
| /freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/ |
| H A D | lpc4357-ea4357-devkit.dts | 48 /* vmmc is controlled by sdmmc host internally */
348 sdmmc_pins: sdmmc-pins {
351 function = "sdmmc";
358 function = "sdmmc";
367 function = "sdmmc";
374 function = "sdmmc";
|