| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | brcm,sdhci-iproc.txt | 1 Broadcom IPROC SDHCI controller
4 by mmc.txt and the properties that represent the IPROC SDHCI controller.
7 - compatible : Should be one of the following
8 "brcm,bcm2835-sdhci"
9 "brcm,bcm2711-emmc2"
10 "brcm,sdhci-iproc-cygnus"
11 "brcm,sdhci-iproc"
13 Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
14 bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
16 Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
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| H A D | marvell,xenon-sdhci.txt | 1 Marvell Xenon SDHCI Controller device tree bindings
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
23 - clock-names:
28 - reg:
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| H A D | marvell,xenon-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhc
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| H A D | sdhci-am654.txt | 1 Device Tree Bindings for the SDHCI Controllers present on TI's AM654 SOCs
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
11 - compatible: should be one of:
12 "ti,am654-sdhci-5.1": SDHCI on AM654 device.
13 "ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.
14 "ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.
15 - reg: Must be two entries.
16 - The first should be the sdhci register space
17 - The second should the subsystem/phy register space
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| H A D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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| H A D | nvidia,tegra20-sdhci.txt | 7 by mmc.txt and the properties used by the sdhci-tegra driver.
10 - compatible : should be one of:
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra194
18 - clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
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| H A D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
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| H A D | nvidia,tegra20-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
23 - enum:
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
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| H A D | sdhci-msm.txt | 1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
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| H A D | brcm,iproc-sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom IPROC SDHCI controller
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
12 - Nicolas Saenz Julienne <nsaenz@kernel.org>
15 - $ref: mmc-controller.yaml#
20 - brcm,bcm2835-sdhci
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| H A D | aspeed,sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
16 Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
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| H A D | sdhci-msm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
13 Secure Digital Host Controller Interface (SDHCI) present on
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
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| H A D | arasan,sdhci.txt | 1 Device Tree Bindings for the Arasan SDHCI Controller
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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| H A D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/arasan,sdhci
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| H A D | sdhci-pxa.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schema
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| H A D | sdhci-of-dwcmshc.txt | 4 - compatible: should be one of the following:
5 "snps,dwcmshc-sdhci"
6 - reg: offset and length of the register set for the device.
7 - interrupts: a single interrupt specifier.
8 - clocks: Array of clocks required for SDHCI; requires at least one for
10 - clock-names: Array of names corresponding to clocks property; shall be
14 sdhci2: sdhci@aa0000 {
15 compatible = "snps,dwcmshc-sdhci";
19 bus-width = <8>;
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| H A D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
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| H A D | microchip,dw-sparx5-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml
13 - Lars Povlsen <lars.povlsen@microchip.com>
18 const: microchip,dw-sparx5-sdhci
29 Handle to "core" clock for the sdhci controller.
31 clock-names:
33 - const: core
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| H A D | nuvoton,ma35d1-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nuvoton,ma35d1-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shan-Chun Hung <shanchun1218@gmail.com>
13 - $ref: sdhci-common.yaml#
18 - nuvoton,ma35d1-sdhci
29 pinctrl-names:
32 - const: default
33 - const: state_uhs
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| H A D | sprd,sdhci-r11.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SDHCI controller
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
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| /freebsd/sys/arm/ti/ |
| H A D | ti_sdhci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
57 #include <dev/sdhci/sdhci.h>
58 #include <dev/sdhci/sdhci_fdt_gpio.h>
90 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
93 {"ti,am335-sdhci", 1},
94 {"ti,omap3-hsmmc", 1},
95 {"ti,omap4-hsmmc", 1},
102 * the device's memory map, followed by the standard sdhci register block.
105 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | mvebu-gated-clock.txt | 12 -----------------------------------
21 17 sdio SDHCI Host
29 -----------------------------------
35 8 audio Audio Cntrl
40 17 sdio SDHCI Host
56 -----------------------------------
64 8 pex0 PCIe 0
83 -----------------------------------
87 8 pex0 PCIe 0
97 -----------------------------------
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| /freebsd/sys/dev/sdhci/ |
| H A D | fsl_sdhci.c | 1 /*-
29 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families.
72 #include <dev/sdhci/sdhci.h>
73 #include <dev/sdhci/sdhci_fdt_gpio.h>
105 * Freescale-specific registers, or in some cases the layout of bits within the
106 * sdhci-defined register is different on Freescale. These names all begin with
112 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
113 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8)
127 #define SDHC_PRES_WTA (1 << 8)
150 #define SDHC_PROT_SDMA (0 << 8)
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| /freebsd/sys/arm/nvidia/ |
| H A D | tegra_sdhci.c | 1 /*-
29 * SDHCI driver glue for NVIDIA Tegra family
58 #include <dev/sdhci/sdhci.h>
59 #include <dev/sdhci/sdhci_fdt_gpio.h>
67 #define VENDOR_CLOCK_CNTRL_CLK_SHIFT 8
95 {"nvidia,tegra124-sdhci", 1},
96 {"nvidia,tegra210-sdhci", 1},
122 return (bus_read_4(sc->mem_res, off)); in RD4()
131 return (bus_read_1(sc->mem_res, off)); in tegra_sdhci_read_1()
140 return (bus_read_2(sc->mem_res, off)); in tegra_sdhci_read_2()
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_sdhci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 #include <dev/sdhci/sdhci.h>
78 ((((NUM_DMA_SEGS * BCM_SDHCI_BUFFER_SIZE) - 1) / PAGE_SIZE) + 1)
83 ((slot)->curcmd->data->len - (slot)->offset)
95 TUNABLE_INT("hw.bcm2835.sdhci.debug", &bcm2835_sdhci_debug);
97 &bcm2835_sdhci_debug, 0, "bcm2835 SDHCI debug level");
121 .clock_src = -1,
131 .clock_src = -1,
138 {"broadcom,bcm2835-sdhci", (uintptr_t)&bcm2835_sdhci_conf},
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