Searched +full:sdfec +full:- +full:code (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx SDFEC(16nm) IP10 - Cvetic, Dragan <dragan.cvetic@amd.com>11 - Erim, Salih <salih.erim@amd.com>14 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block15 which provides high-throughput LDPC and Turbo Code implementations.17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Xilinx SDFEC32 /* Xilinx SDFEC Register Map */65 /* Write Only - Interrupt Enable Register */67 /* Write Only - Interrupt Disable Register */69 /* Read Only - Interrupt Mask Register */101 /* Write Only - ECC Interrupt Enable Register */103 /* Write Only - ECC Interrupt Disable Register */105 /* Read Only - ECC Interrupt Mask Register */111 /* Turbo Code Register */[all …]
1 .. SPDX-License-Identifier: GPL-2.0+4 Xilinx SD-FEC Driver10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.15 …f SD-FEC core features, see the `SD-FEC Product Guide (PG256) <https://www.xilinx.com/cgi-bin/docs…19 - Retrieval of the Integrated Block configuration and status information20 - Configuration of LDPC codes21 - Configuration of Turbo decoding22 - Monitoring errors24 Missing features, known issues, and limitations of the SD-FEC driver are as27 - Only allows a single open file handler to any instance of the driver at any time[all …]