Home
last modified time | relevance | path

Searched full:scc (Results 1 – 25 of 126) sorted by relevance

123456

/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
20 - fsl,mpc885-scc-qmc
21 - fsl,mpc866-scc-qmc
22 - const: fsl,cpm1-scc-qmc
26 - description: SCC (Serial communication controller) register base
27 - description: SCC parameter ram base
38 description: SCC interrupt line in the CPM interrupt controller
107 - fsl,mpc885-scc-qmc-hdlc
108 - fsl,mpc866-scc-qmc-hdlc
109 - const: fsl,cpm1-scc-qmc-hdlc
[all …]
H A Dserial.txt6 - fsl,cpm1-scc-uart
7 - fsl,cpm2-scc-uart
23 compatible = "fsl,mpc8272-scc-uart",
24 "fsl,cpm2-scc-uart";
/linux/net/unix/
H A Dgarbage.c354 * another SCC. in unix_vertex_dead()
360 /* No receiver exists out of the same SCC. */ in unix_vertex_dead()
376 static bool unix_scc_dead(struct list_head *scc, bool fast) in unix_scc_dead() argument
384 list_for_each_entry_reverse(vertex, scc, scc_entry) { in unix_scc_dead()
396 /* If MSG_PEEK intervened, defer this SCC to the next round. */ in unix_scc_dead()
403 static void unix_collect_skb(struct list_head *scc, struct sk_buff_head *hitlist) in unix_collect_skb() argument
407 list_for_each_entry_reverse(vertex, scc, scc_entry) { in unix_collect_skb()
436 static bool unix_scc_cyclic(struct list_head *scc) in unix_scc_cyclic() argument
441 /* SCC containing multiple vertices ? */ in unix_scc_cyclic()
442 if (!list_is_singular(scc)) in unix_scc_cyclic()
[all …]
/linux/drivers/net/ethernet/freescale/fs_enet/
H A Dmac-scc.c3 * Ethernet on Serial Communications Controller (SCC) driver for Motorola MPC8xx and MPC82xx.
75 * Delay to wait for SCC reset command to complete (in us)
94 fep->scc.sccp = of_iomap(ofdev->dev.of_node, 0); in do_pd_setup()
95 if (!fep->scc.sccp) in do_pd_setup()
98 fep->scc.ep = of_iomap(ofdev->dev.of_node, 1); in do_pd_setup()
99 if (!fep->scc.ep) { in do_pd_setup()
100 iounmap(fep->scc.sccp); in do_pd_setup()
117 fep->scc.hthi = 0; in setup_data()
118 fep->scc.htlo = 0; in setup_data()
159 scc_t __iomem *sccp = fep->scc.sccp; in set_promiscuous_mode()
[all …]
/linux/arch/arm/mach-versatile/
H A Dtc2_pm.c29 /* SCC conf registers */
39 static void __iomem *scc; variable
118 return !(readl_relaxed(scc + RESET_CTRL) & mask); in tc2_core_in_reset()
134 readl_relaxed(scc + RESET_CTRL)); in tc2_pm_wait_for_powerdown()
209 * SCC registers. We need to extract runtime information like in tc2_pm_init()
213 "arm,vexpress-scc,v2p-ca15_a7"); in tc2_pm_init()
214 scc = of_iomap(np, 0); in tc2_pm_init()
215 if (!scc) in tc2_pm_init()
218 a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; in tc2_pm_init()
219 a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; in tc2_pm_init()
[all …]
/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl-imx-scc.yaml4 $id: http://devicetree.org/schemas/crypto/fsl-imx-scc.yaml#
7 title: Freescale Security Controller (SCC)
14 const: fsl,imx25-scc
21 - description: SCC SCM interrupt
22 - description: SCC SMN interrupt
48 compatible = "fsl,imx25-scc";
/linux/arch/powerpc/include/asm/
H A Dhydra.h47 char SCC[0x1000]; member
61 #define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
63 #define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
64 #define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
66 #define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
H A Dcpm1.h277 /* SCC Event and Mask register.
363 /* SCC Event register as used by Ethernet.
372 /* SCC Mode Register (PMSR) as used by Ethernet.
388 /* SCC as UART
418 /* SCC Event and Mask registers when it is used as a UART.
432 /* The SCC PMSR when used as a UART.
448 /* CPM Transparent mode SCC.
552 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
/linux/arch/powerpc/boot/
H A Dcpm-serial.c74 static struct cpm_scc *scc; variable
119 out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30); in scc_disable_port()
130 out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30); in scc_enable_port()
210 } else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) { in cpm_console_init()
239 scc = vreg[0]; in cpm_console_init()
/linux/Documentation/devicetree/bindings/hwinfo/
H A Dvia,vt8500-scc-id.yaml4 $id: http://devicetree.org/schemas/hwinfo/via,vt8500-scc-id.yaml#
21 - const: via,vt8500-scc-id
35 compatible = "via,vt8500-scc-id";
/linux/arch/m68k/include/asm/
H A Dmac_iop.h91 struct { /* SCC registers */
92 __u8 sccb_cmd; /* SCC B command reg */
94 __u8 scca_cmd; /* SCC A command reg */
96 __u8 sccb_data; /* SCC B data */
98 __u8 scca_data; /* SCC A data */
H A Dmac_via.h39 #define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
40 * [CHRP] SCC WREQ: Reflects the state of the
41 * Wait/Request pins from the SCC.
48 * signal from port B of the SCC appear on
70 * signal from port A of the SCC appear
77 * drive the SCC's /RTxCA pin.
79 * the SCC cell.
H A Datarihw.h96 ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
97 ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
105 ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
438 ** SCC Z8530
442 struct SCC struct
452 # define atari_scc ((*(volatile struct SCC*)SCC_BAS)) argument
455 # define st_escc ((*(volatile struct SCC*)0xfffffa31))
458 /* TT SCC DMA Controller (same chip as SCSI DMA) */
H A Dmac_psc.h6 * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
18 * 5. SCC Channel A Receive
19 * 6. SCC Channel B Receive
20 * 7. SCC Channel A Transmit
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm216 s_getreg_b32 s_save_status, hwreg(S_STATUS_HWREG) //save STATUS since we will change SCC
643 s_cmp_lt_u32 m0, 96 //scc = (m0 < first 96 SGPR) ? 1 : 0
723 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0
743 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0
761 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0
781 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0
850 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0
895 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0
931 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0
995 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0
[all …]
H A Dcwsr_trap_handler_gfx8.asm164 …ave_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC
177 set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)
188 set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)
331 …s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_sa…
457 …s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_sa…
521 …s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_…
558 …s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m…
605 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0
664 …set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed …
703 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc
/linux/Documentation/networking/devlink/
H A Dhns3.rst26 * - ``fw.scc``
29 SCC is a firmware component which provides multiple RDMA congestion
/linux/arch/m68k/mac/
H A Dmacints.c34 * 4 - SCC
63 * 4 - SCC IOP
73 * - slot 1: SCC channel A interrupt
74 * - slot 2: SCC channel B interrupt
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,cpm-enet.yaml16 - fsl,cpm1-scc-enet
17 - fsl,cpm2-scc-enet
/linux/arch/m68k/atari/
H A Dconfig.c77 /* ++roman: This is a more elaborate test for an SCC chip, since the plain
78 * Medusa board generates DTACK at the SCC's standard addresses, but a SCC
309 ATARIHW_SET(SCC); in config_atari()
310 pr_cont(" SCC"); in config_atari()
632 ATARIHW_ANNOUNCE(SCC, "Serial Communications Controller SCC 8530"); in atari_get_hardware_list()
633 ATARIHW_ANNOUNCE(ST_ESCC, "Extended Serial Communications Controller SCC 85230"); in atari_get_hardware_list()
639 ATARIHW_ANNOUNCE(SCC_DMA, "DMA Controller for SCC"); in atari_get_hardware_list()
H A Dataints.c17 * Corrected a bug in atari_add_isr() which rejected all SCC
63 * TT-MFP, SCC, and finally VME interrupts. Vector numbers for the latter can
296 if (ATARIHW_PRESENT(SCC) && !atari_SCC_reset_done) { in atari_init_IRQ()
305 tt_scu.vme_mask = 0x60; /* enable MFP and SCC ints */ in atari_init_IRQ()
/linux/arch/mips/include/asm/dec/
H A Dkn02ba.h34 #define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
35 #define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
H A Dioasic_addrs.h30 #define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
32 #define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */
111 * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
/linux/arch/powerpc/boot/dts/
H A Dksi8560.dts254 compatible = "fsl,mpc8560-scc-uart",
255 "fsl,cpm2-scc-uart";
266 compatible = "fsl,mpc8560-scc-uart",
267 "fsl,cpm2-scc-uart";
/linux/include/soc/fsl/
H A Dcpm.h116 * Common to SCC and FCC.
135 * Common to SCC and FCC.
152 /* Buffer descriptor control/status used by Transparent mode SCC.

123456