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/freebsd/share/doc/smm/02.config/
H A Dc.t91 controller sc0 at uba? csr 0176700 vector upintr
92 disk up0 at sc0 drive 0
93 disk up1 at sc0 drive 1
H A D5.t211 controller sc0 at uba? csr 0176700 vector upintr
212 disk up0 at sc0 drive 0
213 disk up1 at sc0 drive 1
222 to memory or cpu cycles. The extra UNIBUS controller, ``sc0'',
H A Dspell.ok238 sc0
/freebsd/sys/dev/uart/
H A Duart_core.c580 struct uart_softc *sc, *sc0; in uart_bus_attach() local
590 sc0 = device_get_softc(dev); in uart_bus_attach()
591 if (sc0->sc_class->size > device_get_driver(dev)->size) { in uart_bus_attach()
592 sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO); in uart_bus_attach()
593 bcopy(sc0, sc, sizeof(*sc)); in uart_bus_attach()
596 sc = sc0; in uart_bus_attach()
/freebsd/sys/dev/scc/
H A Dscc_core.c103 struct scc_softc *sc, *sc0; in scc_bfe_attach() local
115 sc0 = device_get_softc(dev); in scc_bfe_attach()
116 cl = sc0->sc_class; in scc_bfe_attach()
119 bcopy(sc0, sc, sizeof(*sc)); in scc_bfe_attach()
122 sc = sc0; in scc_bfe_attach()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td868 … // gfx940: bit 0 = sc0, bit 1 = nt, bit 4 = sc1
1102 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1132 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1162 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1194 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1212 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1231 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1249 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1269 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
1288 // gfx940: bit 0 = sc0, bit 1 = nt, bit 3 = swz, bit 4 = sc1
[all …]
/freebsd/share/man/man4/
H A Dukbd.4113 .Dl "device sc0 at isa? flags 0x100"
H A Dhkbd.4117 .Dl "device sc0 at isa? flags 0x100"
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Drealtek,rtd1319d-pinctrl.yaml54 enum: [ gpio, nf, emmc, tp0, tp1, sc0, sc0_data0, sc0_data1, sc0_data2,
H A Drealtek,rtd1619b-pinctrl.yaml59 pwm3, etn_led, etn_phy, etn_clk, sc0, vfd, gspi_loc0, iso_gspi_loc0, pcie1,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp482 /// Sets SC0 bit to "true" if present in \p MI. Returns true if \p MI
485 return enableNamedBit(MI, AMDGPU::CPol::SC0); in enableSC0Bit()
1562 .addImm(AMDGPU::CPol::SC0 | AMDGPU::CPol::SC1); in insertRelease()
1689 // to indicate system or agent scope. The SC0 bit is used to indicate if in enableRMWCacheBypass()
1764 .addImm(AMDGPU::CPol::SC0 | AMDGPU::CPol::SC1); in insertAcquire()
1796 .addImm(AMDGPU::CPol::SC0); in insertAcquire()
1851 .addImm(AMDGPU::CPol::SC0 | AMDGPU::CPol::SC1); in insertRelease()
H A DAMDGPU.td920 def FeatureForceStoreSC0SC1 : SubtargetFeature<"force-store-sc0-sc1",
923 "Has SC0 and SC1 on stores"
H A DSIDefines.h384 SC0 = GLC, enumerator
/freebsd/lib/libusb/
H A Dlibusb20.h227 void libusb20_tr_set_priv_sc0(struct libusb20_transfer *xfer, void *sc0);
H A Dlibusb20.c386 libusb20_tr_set_priv_sc0(struct libusb20_transfer *xfer, void *sc0) in libusb20_tr_set_priv_sc0() argument
388 xfer->priv_sc0 = sc0; in libusb20_tr_set_priv_sc0()
H A Dlibusb20.385 .Fn libusb20_tr_set_priv_sc0 "struct libusb20_transfer *xfer" "void *sc0"
/freebsd/contrib/file/magic/Magdir/
H A Dprinter256 # like: "IN;" "DF;IN;LT;PU1000,1000;PD2000,10" "SP6;DI0,1;SR0.70,1.90;SC0,800,"
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp2055 unsigned SC0 = storageClassToAddressSpace(SPIRV::StorageClass::Function); in getOrCreateSPIRVDeviceEventPointer() local
2057 Type *PtrType = PointerType::get(PointerType::get(OpaqueType, SC0), SC1); in getOrCreateSPIRVDeviceEventPointer()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4948 Error(IDLoc, isGFX940() ? "instruction must use sc0" in validateCoherencyBits()
4957 &CStr.data()[CStr.find(isGFX940() ? "sc0" : "glc")]); in validateCoherencyBits()
4958 Error(S, isGFX940() ? "instruction must not use sc0" in validateCoherencyBits()
6516 .Case("sc0", AMDGPU::CPol::SC0) in getCPolKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp197 !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0" in printCPol()
/freebsd/sys/dev/syscons/
H A Dsyscons.c2671 DPRINTF(5, ("sc0: sc_switch_scr() %d ", next_scr + 1)); in sc_switch_scr()