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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-sata.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 sata {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges = <0x0 0x0 0x67d00000 0x00800000>;
39 sata0: ahci@0 {
40 compatible = "brcm,iproc-ahci", "generic-ahci";
41 reg = <0x00000000 0x1000>;
42 reg-names = "ahci";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dnvidia,tegra-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dexynos-sata.txt1 * Samsung AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
7 - compatible : compatible list, contains "samsung,exynos5-sata"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - samsung,sata-freq : <frequency in MHz>
11 - phys : Must contain exactly one entry as specified
12 in phy-bindings.txt
13 - phy-names : Must be "sata-phy"
[all …]
H A Dsata-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial AT attachment (SATA) controllers
10 - Linus Walleij <linus.walleij@linaro.org>
14 AT attachment (SATA) storage devices. It doesn't constitute a device tree
18 The SATA controller-specific device tree bindings are responsible for
23 pattern: "^sata(@.*)?$"
25 Specifies the host controller node. SATA host controller nodes are named
[all …]
H A Drenesas,rcar-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Serial-ATA Interface
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,sata-r8a7779 # R-Car H1
18 - items:
[all …]
H A Dahci-platform.txt1 * AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
6 It is possible, but not required, to represent each port as a sub-node.
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
16 - "marvell,armada-380-ahci"
[all …]
H A Dcortina,gemini-sata-bridge.txt1 * Cortina Systems Gemini SATA Bridge
3 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
5 them in different configurations to two SATA ports.
8 - compatible: should be
9 "cortina,gemini-sata-bridge"
10 - reg: registers and size for the block
11 - resets: phandles to the reset lines for both SATA bridges
12 - reset-names: must be "sata0", "sata1"
13 - clocks: phandles to the compulsory peripheral clocks
14 - clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
[all …]
H A Dfsl-sata.txt1 * Freescale 8xxx/3.0 Gb/s SATA nodes
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA port should have its own node.
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
10 "fsl,pq-sata"
11 - interrupts : <interrupt mapping for SATA IRQ>
12 - cell-index : controller index.
13 1 for controller @ 0x18000
14 2 for controller @ 0x19000
[all …]
H A Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini SATA Bridge
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
15 them in different configurations to two SATA ports.
19 const: cortina,gemini-sata-bridge
26 description: phandles to the reset lines for both SATA bridges
[all …]
H A Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
[all …]
H A Dimx-sata.txt1 * Freescale i.MX AHCI SATA Controller
3 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
7 - compatible : should be one of the following:
8 - "fsl,imx53-ahci" for i.MX53 SATA controller
9 - "fsl,imx6q-ahci" for i.MX6Q SATA controller
10 - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
11 - interrupts : interrupt mapping for SATA IRQ
12 - reg : registers mapping
13 - clocks : list of clock specifiers, must contain an entry for each
14 required entry in clock-names
[all …]
H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
[all …]
H A Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
[all …]
H A Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
[all …]
H A Dqcom-sata.txt1 * Qualcomm AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
[all …]
H A Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
[all …]
H A Dmarvell.txt1 * Marvell Orion SATA
4 - compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
5 - reg : Address range of controller
6 - interrupts : Interrupt controller is using
7 - nr-ports : Number of SATA ports in use.
10 - phys : List of phandles to sata phys
11 - phy-names : Should be "0", "1", etc, one number per phandle
15 sata@80000 {
16 compatible = "marvell,orion-sata";
17 reg = <0x80000 0x5000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dbrcm-sata-phy.txt4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
[all …]
H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
[all …]
H A Dphy-miphy365x.txt5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
24 - PHY_TYPE_PCI
25 - reg : Address and length of register sets for each device in
[all …]
H A Dqcom-ipq806x-sata-phy.txt1 Qualcomm IPQ806x SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: must be exactly one entry
12 - clock-names: must be "cfg"
15 sata_phy: sata-phy@1b400000 {
[all …]
H A Dqcom-apq8064-sata-phy.txt1 Qualcomm APQ8064 SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,apq8064-sata-phy".
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
12 clock-names.
13 - clock-names: must be "cfg" for phy config clock.
[all …]
H A Dphy-mvebu.txt1 * Marvell MVEBU SATA PHY
3 Power control for the SATA phy found on Marvell MVEBU SoCs.
5 This document extends the binding described in phy-bindings.txt
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
17 reg = <0x84000 0x0334>;
[all …]
H A Dqcom,sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SATA PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
14 The Qualcomm SATA PHY describes on-chip SATA Physical layer controllers.
19 - qcom,ipq806x-sata-phy
20 - qcom,apq8064-sata-phy
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
13 0 Audio AC97 Cntrl
14 1 pex0_en PCIe 0 Clock out
17 4 ge0 Gigabit Ethernet 0
18 5 pex0 PCIe Cntrl 0
20 15 sata0 SATA Host 0
25 30 sata1 SATA Host 0
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
37 14 sata0_link SATA 0 Link
[all …]

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