Searched +full:sar2130p +full:- +full:mdss (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/gpu/drm/msm/ |
| H A D | msm_mdss.c | 2 * SPDX-License-Identifier: GPL-2.0
23 #include <generated/mdss.xml.h>
56 path0 = devm_of_icc_get(dev, "mdp0-mem"); in msm_mdss_parse_data_bus_icc_path()
60 msm_mdss->mdp_path[0] = path0; in msm_mdss_parse_data_bus_icc_path()
61 msm_mdss->num_mdp_paths = 1; in msm_mdss_parse_data_bus_icc_path()
63 path1 = devm_of_icc_get(dev, "mdp1-mem"); in msm_mdss_parse_data_bus_icc_path()
65 msm_mdss->mdp_path[1] = path1; in msm_mdss_parse_data_bus_icc_path()
66 msm_mdss->num_mdp_paths++; in msm_mdss_parse_data_bus_icc_path()
69 reg_bus_path = of_icc_get(dev, "cpu-cfg"); in msm_mdss_parse_data_bus_icc_path()
71 msm_mdss->reg_bus_path = reg_bus_path; in msm_mdss_parse_data_bus_icc_path()
[all …]
|
| /linux/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu-qcom.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
17 #define QCOM_DUMMY_VAL -1
20 * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
38 { .compatible = "qcom,adreno-gmu",
40 { .compatible = "qcom,adreno-smmu",
44 { .compatible = "qcom,sc7280-mdss",
46 { .compatible = "qcom,sc7280-venus",
[all …]
|
| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_kms.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
13 #include <linux/dma-buf.h>
66 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
69 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
76 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
79 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
80 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, in _dpu_danger_signal_status()
84 if (kms->hw_mdp->ops.get_safe_status) in _dpu_danger_signal_status()
[all …]
|