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/linux/lib/crypto/powerpc/
H A Dsha256-spe-asm.S114 rotrwi rT0,a,2; /* 1: S0 = a rotr 2 */ \
116 rotrwi rT1,a,13; /* 1: S0' = a rotr 13 */ \
118 rotrwi rT3,a,22; /* 1: S0" = a rotr 22 */ \
119 xor rT0,rT0,rT1; /* 1: S0 = S0 xor S0' */ \
121 xor rT3,rT0,rT3; /* 1: S0 = S0 xor S0" */ \
129 add rT3,rT3,rT2; /* 1: temp2 = S0 + maj */ \
141 rotrwi rT0,h,2; /* 2: S0 = a rotr 2 */ \
143 rotrwi rT1,h,13; /* 2: S0' = a rotr 13 */ \
145 rotrwi rT3,h,22; /* 2: S0" = a rotr 22 */ \
146 xor rT0,rT0,rT1; /* 2: S0 = S0 xor S0' */ \
[all …]
/linux/arch/loongarch/kernel/
H A Drelocate_kernel.S26 move s0, a4
32 beqz s0, done
35 PTR_L s1, s0, 0
36 PTR_ADDI s0, s0, SZREG
46 /* indirection page, update s0 */
50 and s0, s1, t0
99 iocsrrd.w s0, t1 /* check PC as an indicator */
100 beqz s0, 1b
101 iocsrrd.d s0, t1 /* get PC via mailbox */
104 or s0, s0, t0 /* s0 = TO_CACHE(s0) */
[all …]
H A Dmcount.S21 PTR_S s0, sp, MCOUNT_S0_OFFSET
23 move s0, a0
27 move a0, s0
29 PTR_L s0, sp, MCOUNT_S0_OFFSET
42 move a1, s0 /* arg1: parent's return address */
74 move a2, s0 /* arg2: Callsite parent ra */
/linux/arch/riscv/kernel/
H A Dentry.S149 REG_L s0, TASK_TI_USER_SP(tp)
155 REG_S s0, PT_SP(sp)
214 REG_L s0, PT_STATUS(sp)
218 and s0, s0, t0
220 andi s0, s0, SR_SPP
222 bnez s0, 1f
229 addi s0, sp, PT_SIZE_ON_STACK
230 REG_S s0, TASK_TI_KERNEL_SP(tp)
305 REG_L s0, TASK_TI_KERNEL_SP(tp)
311 REG_S s0, PT_SP(sp)
[all …]
H A Dmcount.S19 REG_S s0, 0*SZREG(sp)
21 addi s0, sp, 16
31 REG_S s0, FREGS_S0(sp)
34 addi s0, sp, FREGS_SIZE_ON_STACK
39 REG_L s0, 0*SZREG(sp)
45 REG_L s0, FREGS_S0(sp)
67 * s0 (frame pointer, if enabled) on entry and the sp (stack pointer) on return.
71 * value stored in -16(s0) on entry, and the s0 on return.
106 addi a0, s0, -SZREG
109 REG_L a2, -2*SZREG(s0)
[all …]
H A Dkexec_relocate.S16 * s0: Pointer to the current entry
24 mv s0, a0
59 REG_L t0, 0(s0) /* t0 = *image->entry */
60 addi s0, s0, RISCV_SZPTR /* image->entry++ */
72 andi s0, t0, ~0x2
113 mv s0, zero
153 * s0: (const) Phys address to jump to
157 mv s0, a1
168 mv a2, s0
177 mv s0, zero
/linux/lib/crypto/x86/
H A Dsha512-avx2-asm.S199 xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
200 rorx $28, a, T1 # T1 = (a >> 28) # S0
203 xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
209 add y1, h # h = k + w + h + S0 # --
213 add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
214 add y3, h # h = t1 + S0 + MAJ # --
226 vpxor YTMP1, YTMP3, YTMP1 # YTMP1 = s0
230 vpaddq YTMP1, YTMP0, YTMP0 # YTMP0 = W[-16] + W[-7] + s0
232 vperm2f128 $0x0, YTMP0, YTMP0, Y_0 # Y_0 = W[-16] + W[-7] + s0 {BABA}
234 vpand MASK_YMM_LO(%rip), YTMP0, YTMP0 # YTMP0 = W[-16] + W[-7] + s0 {DC00}
[all …]
H A Dsha256-avx2-asm.S178 xor T1, y1 # y1 = (a>>22) ^ (a>>13) # S0
179 rorx $2, a, T1 # T1 = (a >> 2) # S0
183 xor T1, y1 # y1 = (a>>22) ^ (a>>13) ^ (a>>2) # S0
190 add y1, h # h = k + w + h + S0 # --
196 add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
197 add y3, h # h = t1 + S0 + MAJ # --
227 xor T1, y1 # y1 = (a>>22) ^ (a>>13) # S0
230 rorx $2, a, T1 # T1 = (a >> 2) # S0
234 xor T1, y1 # y1 = (a>>22) ^ (a>>13) ^ (a>>2) # S0
239 vpxor XTMP4, XTMP3, XTMP1 # XTMP1 = s0
[all …]
H A Dsha256-avx-asm.S154 ## compute s0 four at a time and s1 two at a time
171 ## compute s0
176 MY_ROR 2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
188 add y1, h # h = h + S1 + CH + k + w + S0
191 add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
214 MY_ROR 2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
219 vpxor XTMP4, XTMP3, XTMP1 # XTMP1 = s0
226 add y1, h # h = h + S1 + CH + k + w + S0
227 vpaddd XTMP1, XTMP0, XTMP0 # XTMP0 = W[-16] + W[-7] + s0
229 add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
[all …]
H A Dsha256-ssse3-asm.S148 ## compute s0 four at a time and s1 two at a time
166 ## compute s0
172 ror $2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
185 add y1, h # h = h + S1 + CH + k + w + S0
188 add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
214 ror $2, y1 # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
219 pxor XTMP4, XTMP1 # XTMP1 = s0
226 add y1, h # h = h + S1 + CH + k + w + S0
227 paddd XTMP1, XTMP0 # XTMP0 = W[-16] + W[-7] + s0
229 add y0, h # h = h + S1 + CH + k + w + S0 + MAJ
[all …]
/linux/drivers/soc/bcm/brcmstb/pm/
H A Ds2-mips.S24 sw s0, 4(sp)
35 * s0: AON_CTRL base register
44 lw s0, 0(t0)
79 sw zero, AON_CTRL_PM_CTRL(s0)
80 lw zero, AON_CTRL_PM_CTRL(s0)
81 sw t0, AON_CTRL_PM_CTRL(s0)
82 lw t0, AON_CTRL_PM_CTRL(s0)
134 sw t1, AON_CTRL_HOST_MISC_CMDS(s0)
135 lw t1, AON_CTRL_HOST_MISC_CMDS(s0)
137 sw zero, AON_CTRL_PM_CTRL(s0)
[all …]
/linux/net/dccp/ccids/lib/
H A Dpacket_history.c
/linux/arch/x86/crypto/
H A Dsm4-aesni-avx-asm_64.S188 #define ROUND(round, s0, s1, s2, s3) \ argument
201 vpxor RTMP0, s0, s0; /* s0 ^ x */ \
207 vpxor RTMP1, s0, s0; /* s0 ^ x ^ rol(x,24) */ \
210 vpxor RTMP0, s0, s0; \
211 /* s0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
212 vpxor RTMP1, s0, s0;
276 #define ROUND(round, s0, s1, s2, s3, r0, r1, r2, r3) \ argument
301 vpxor RTMP0, s0, s0; /* s0 ^ x */ \
316 vpxor RTMP1, s0, s0; /* s0 ^ x ^ rol(x,24) */ \
317 /* s0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-ampere-mtjade.dts117 channels = "s0", "s1";
126 channels = "s0", "s1";
135 channels = "s0", "s1";
144 channels = "s0", "s1";
153 channels = "s0", "s1";
162 channels = "s0", "s1";
171 channels = "s0", "s1";
180 channels = "s0", "s1";
189 channels = "s0", "s1";
198 channels = "s0", "s1";
[all …]
/linux/arch/arm64/crypto/
H A Dsm3-ce-core.S44 .macro round, ab, s0, t0, t1, i
49 sm3tt2\ab v9.4s, v5.4s, \s0\().4s, \i
52 .macro qround, ab, s0, s1, s2, s3, s4
55 ext v6.16b, \s0\().16b, \s1\().16b, #12
57 sm3partw1 \s4\().4s, \s0\().4s, \s3\().4s
60 eor v10.16b, \s0\().16b, \s1\().16b
62 round \ab, \s0, v11, v12, 0
63 round \ab, \s0, v12, v11, 1
64 round \ab, \s0, v11, v12, 2
65 round \ab, \s0, v12, v11, 3
H A Dsm4-neon-core.S40 #define transpose_4x4(s0, s1, s2, s3) \ argument
41 zip1 RTMP0.4s, s0.4s, s1.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
45 zip1 s0.2d, RTMP0.2d, RTMP1.2d; \
50 #define transpose_4x4_2x(s0, s1, s2, s3, s4, s5, s6, s7) \ argument
51 zip1 RTMP0.4s, s0.4s, s1.4s; \
53 zip2 RTMP2.4s, s0.4s, s1.4s; \
59 zip1 s0.2d, RTMP0.2d, RTMP1.2d; \
68 #define rotate_clockwise_4x4(s0, s1, s2, s3) \ argument
69 zip1 RTMP0.4s, s1.4s, s0.4s; \
[all …]
/linux/arch/mips/kernel/
H A Drelocate_kernel.S22 PTR_L s0, kexec_indirection_page
26 PTR_L s2, (s0)
27 PTR_ADDIU s0, s0, SZREG
42 /* indirection page, update s0 */
45 and s0, s2, ~0x2
126 1: LONG_L s0, (t0)
127 bne s0, zero,1b
/linux/lib/crypto/arm/
H A Dsha256-ce.S32 .macro add_only, ev, s0 argument
34 .ifnb \s0
39 .ifnb \s0
40 vadd.u32 ta\ev, q\s0, k\ev
44 .macro add_update, ev, s0, s1, s2, s3
45 sha256su0.32 q\s0, q\s1
47 sha256su1.32 q\s0, q\s2, q\s3
H A Dsha1-ce-core.S36 .macro add_only, op, ev, rc, s0, dg1
37 .ifnb \s0
38 vadd.u32 tb\ev, q\s0, \rc
48 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
49 sha1su0.32 q\s0, q\s1, q\s2
51 sha1su1.32 q\s0, q\s3
/linux/lib/crypto/arm64/
H A Dsha1-ce-core.S34 .macro add_only, op, ev, rc, s0, dg1
36 add t1.4s, v\s0\().4s, \rc\().4s
44 .ifnb \s0
45 add t0.4s, v\s0\().4s, \rc\().4s
52 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
53 sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
55 sha1su1 v\s0\().4s, v\s3\().4s
/linux/arch/mips/include/asm/mach-loongson64/
H A Dkernel-entry-init.h80 /* s0:prid s1:initfn */
87 mfc0 s0, CP0_PRID
88 andi s0, s0, (PRID_IMP_MASK | PRID_REV_MASK)
89 beq s0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1), 1f
90 beq s0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R2), 1f
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_1_10_cleaner_shader.asm52 …s_cmp_eq_u32 s0, 1 // Bit0 is set, sgpr0 is set then clear VGPRS an…
53 … label_0023 // Clean VGPRs and LDS if sgpr0 of wave is set, scc = (s0 == 1)
101 s_movreld_b32 s0, s0
102 s_movreld_b32 s1, s0
103 s_movreld_b32 s2, s0
104 s_movreld_b32 s3, s0
/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl.c1364 dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512 in spl_set_easf_data()
1367 dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20 in spl_set_easf_data()
1370 dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 in spl_set_easf_data()
1373 dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 in spl_set_easf_data()
1376 dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4 in spl_set_easf_data()
1379 dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5 in spl_set_easf_data()
1382 dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6 in spl_set_easf_data()
1385 dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7 in spl_set_easf_data()
1389 dscl_prog_data->easf_v_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 in spl_set_easf_data()
1393 dscl_prog_data->easf_v_bf3_pwl_base_set1 = 62; // S0.6, BF3 Base PWL Segment 1 in spl_set_easf_data()
[all …]
/linux/kernel/trace/rv/monitors/sleep/
H A Dsleep.h64 S0, enumerator
115 __set_bit(S0, mon->states); in ltl_start()
164 case S0: in ltl_possible_next_states()
166 __set_bit(S0, next); in ltl_possible_next_states()
204 __set_bit(S0, next); in ltl_possible_next_states()
214 __set_bit(S0, next); in ltl_possible_next_states()
224 __set_bit(S0, next); in ltl_possible_next_states()
248 __set_bit(S0, next); in ltl_possible_next_states()
/linux/kernel/trace/rv/monitors/pagefault/
H A Dpagefault.h32 S0, enumerator
46 __set_bit(S0, mon->states); in ltl_start()
59 case S0: in ltl_possible_next_states()
61 __set_bit(S0, next); in ltl_possible_next_states()

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