Home
last modified time | relevance | path

Searched +full:rzg2l +full:- +full:tsu (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/thermal/
H A Drzg2l-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/rzg2l-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 On RZ/G2L SoCs, the thermal sensor unit (TSU) measures the
14 - Biju Das <biju.das.jz@bp.renesas.com>
16 $ref: thermal-sensor.yaml#
21 - enum:
22 - renesas,r9a07g043-tsu # RZ/G2UL and RZ/Five
23 - renesas,r9a07g044-tsu # RZ/G2{L,LC}
[all …]
/linux/drivers/thermal/renesas/
H A Drzg2l_thermal.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L TSU Thermal Sensor Driver
67 return ioread32(priv->base + reg); in rzg2l_thermal_read()
73 iowrite32(data, priv->base + reg); in rzg2l_thermal_write()
84 * TSU repeats measurement at 20 microseconds intervals and in rzg2l_thermal_get_temp()
109 val = ((dsensor - priv->calib1) * (MCELSIUS(165) / in rzg2l_thermal_get_temp()
110 (priv->calib0 - priv->calib1))) - MCELSIUS(40); in rzg2l_thermal_get_temp()
129 * Before setting the START bit, TSU should be in normal operating in rzg2l_thermal_init()
130 * mode. As per the HW manual, it will take 60 µs to place the TSU in rzg2l_thermal_init()
139 return readl_poll_timeout(priv->base + TSU_SS, reg_val, in rzg2l_thermal_init()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
[all …]
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
/linux/drivers/clk/renesas/
H A Dr9a07g043-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/r9a07g043-cpg.h>
15 #include "rzg2l-cpg.h"
134 DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
H A Dr9a07g044-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/r9a07g044-cpg.h>
14 #include <dt-bindings/clock/r9a07g054-cpg.h>
16 #include "rzg2l-cpg.h"
170 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),