Searched +full:rz +full:- +full:mtu3 (Results 1 – 13 of 13) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.03 * Renesas RZ/G2L MTU3a PWM Timer driver8 …* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?lang…11 * - When PWM is disabled, the output is driven to Hi-Z.12 * - While the hardware supports both polarities, the driver (for now)14 * - HW uses one counter and two match components to configure duty_cycle16 * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM18 * - MTU{1, 2} channels have a single IO, whereas all other HW channels have20 * - Each IO is modelled as an independent PWM channel.21 * - rz_mtu3_channel_io_map table is used to map the PWM channel to the[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>12 pinctrl-0 = <&sound_clk_pins>;13 pinctrl-names = "default";20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */21 can0-stb-hog {22 gpio-hog;24 output-low;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts8 #include <dt-bindings/gpio/gpio.h>9 #include "rzg2ul-smarc-pinfunction.dtsi"10 #include "rz-smarc-common.dtsi"14 /delete-property/ pinctrl-0;15 /delete-property/ pinctrl-names;21 sound-dai = <&ssi1>;25 clock-frequency = <400000>;30 gpio-controller;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/G2LC SMARC pincontrol parts8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>12 pinctrl-0 = <&sound_clk_pins>;13 pinctrl-names = "default";16 /* SW8 should be at position 2->1 */24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */25 can1-stb-hog {26 gpio-hog;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs8 #include <dt-bindings/clock/r9a07g043-cpg.h>12 #address-cells = <2>;13 #size-cells = <2>;15 audio_clk1: audio1-clk {16 compatible = "fixed-clock";17 #clock-cells = <0>;19 clock-frequency = <0>;22 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/G2UL SMARC pincontrol parts8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>12 pinctrl-0 = <&sound_clk_pins>;13 pinctrl-names = "default";21 can0-stb-hog {22 gpio-hog;24 output-low;25 line-name = "can0_stb";[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g044-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/V2L SoC8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g054-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>17 osc1: cec-clock {18 compatible = "fixed-clock";19 #clock-cells = <0>;20 clock-frequency = <12000000>;23 hdmi-out {24 compatible = "hdmi-connector";[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Renesas RZ/G2L MTU3a Counter driver10 #include <linux/mfd/rz-mtu3.h>40 * 0: 16-bit, 1: 32-bit66 * struct rz_mtu3_cnt - MTU3 counter private data68 * @clk: MTU3 module clock72 * @mtu_16bit_max: Cache for 16-bit counters73 * @mtu_32bit_max: Cache for 32-bit counters102 return &priv->ch[ch_id]; in rz_mtu3_get_ch()110 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_is_counter_invalid()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only6 obj-$(CONFIG_COUNTER) += counter.o7 counter-y := counter-core.o counter-sysfs.o counter-chrdev.o9 obj-$(CONFIG_I8254) += i8254.o10 obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o11 obj-$(CONFIG_INTERRUPT_CNT) += interrupt-cnt.o12 obj-$(CONFIG_RZ_MTU3_CNT) += rz-mtu3-cnt.o13 obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o14 obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o15 obj-$(CONFIG_TI_EQEP) += ti-eqep.o[all …]
1 # SPDX-License-Identifier: GPL-2.0-only31 tristate "ACCES 104-QUAD-8 driver"37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature38 encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).41 operation on the respective count value attribute. The 104-QUAD-858 module will be called ftm-quaddec.69 will be called intel-qep.79 module will be called interrupt-cnt.91 module will be called microchip-tcb-capture.94 tristate "Renesas RZ/G2L MTU3a counter driver"[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */3 * MFD internals for Renesas RZ/G2L MTU3 Core driver