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Searched +full:rx +full:- +full:equalizer (Results 1 – 18 of 18) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Daniel Machon <daniel.machon@microchip.com>
19 * RX Adaptive Decision Feedback Equalizer (DFE)
20 * Programmable continuous time linear equalizer (CTLE)
21 * Rx variable gain control
22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
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H A Dbrcm-sata-phy.txt4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
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H A Dst,stm32mp25-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Bruel <christian.bruel@foss.st.com>
18 const: st,stm32mp25-combophy
23 "#phy-cells":
29 - description: apb Bus clock mandatory to access registers.
30 - description: ker Internal RCC reference clock for USB3 or PCIe
31 - description: pad Optional on board clock input for PCIe only. Typically an
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H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
48 vdda1v1-supply:
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/freebsd/sys/dev/al_eth/
H A Dal_init_eth_kr.c1 /*-
38 * @brief auto-negotiation and link training algorithms and state machines
44 * - preparation - waiting till the link partner (lp) will be ready and
46 * - measurement (per coefficient) - issue decrement for the coefficient
49 * - completion - indicate the receiver is ready and wait for the lp to
54 /* timeout in mSec before auto-negotiation will be terminated */
137 rc = al_eth_kr_an_init(kr_data->adapter, an_adv); in al_eth_kr_an_run()
140 kr_data->adapter->name, __func__); in al_eth_kr_an_run()
144 rc = al_eth_kr_an_start(kr_data->adapter, AL_ETH_AN__LT_LANE_0, in al_eth_kr_an_run()
148 kr_data->adapter->name, __func__); in al_eth_kr_an_run()
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_interface.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
101 * Transmits the untimed, partial equalized RX signal out the transmit
114 * Loops back the TX driver IO signal to the RX IO pins
129 /** Loops TX data (to PMA) to RX path (instead of PMA data) */
178 * Tx de-emphasis parameters
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
198 * 000 - Not Supported
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/freebsd/sys/contrib/dev/iwlwifi/pcie/
H A Dctxt-info-v2.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2018-2025 Intel Corporation
6 #include "iwl-trans.h"
7 #include "iwl-fh.h"
8 #include "iwl-context-info-v2.h"
10 #include "iwl-prph.h"
42 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_ctxt_info_dbg_enable()
46 if (fw_mon->size) { in iwl_pcie_ctxt_info_dbg_enable()
52 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); in iwl_pcie_ctxt_info_dbg_enable()
53 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); in iwl_pcie_ctxt_info_dbg_enable()
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/freebsd/share/misc/
H A Dusb_hid_usages4 # - lines that do not start with a white space give the number and name of
6 # - lines that start with a white space give the number and name of
20 0x08 Multi-axis Controller
25 0x33 Rx
62 0x90 D-pad Up
63 0x91 D-pad Down
64 0x92 D-pad Right
65 0x93 D-pad Left
107 0xB2 Anti-Torque Control
278 0x2D Keyboard - and (underscore)
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H A Dusb_vendors6 # http://www.linux-usb.org/usb-ids.html
7 # or send entries as patches (diff -u old new) in the
10 # http://www.linux-usb.org/usb.ids
13 # Date: 2025-09-15 20:34:02
20 # device device_name <-- single tab
21 # interface interface_name <-- two tabs
38 5301 GW-US54ZGL 802.11bg
54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]
64 0200 TP-Link
86 120e ASI120MC-S Planetary Camera
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/freebsd/usr.sbin/virtual_oss/virtual_oss/
H A Dmain.c1 /*-
2 * Copyright (c) 2012-2022 Hans Petter Selasky
73 uint32_t fmt = pvc->format; in vclient_sample_bytes()
94 if (pvc->tx_busy == 0) in vclient_output_delay()
97 mod = pvc->channels * vclient_sample_bytes(pvc); in vclient_output_delay()
99 size = vring_total_read_len(&pvc->tx_ring[0]); in vclient_output_delay()
102 size = (size * (uint64_t)pvc->sample_rate) / in vclient_output_delay()
104 size += vring_total_read_len(&pvc->tx_ring[1]); in vclient_output_delay()
105 size -= size % mod; in vclient_output_delay()
113 if (pvc->rx_busy == 0) in vclient_input_delay()
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/freebsd/sys/dev/ice/
H A Dice_common.c1 /* SPDX-License-Identifier: BSD-3-Clause */
127 * ice_dump_phy_type - helper function to dump phy_type
158 * ice_set_mac_type - Sets MAC type
168 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) in ice_set_mac_type()
171 switch (hw->device_id) { in ice_set_mac_type()
178 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
199 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
205 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
225 hw->mac_type = ICE_MAC_E830; in ice_set_mac_type()
228 hw->mac_type = ICE_MAC_UNKNOWN; in ice_set_mac_type()
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/freebsd/sys/dev/bxe/
H A Dbxe_elink.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
970 * elink_check_lfa - This function checks if link reinitialization is required,
982 struct bxe_softc *sc = params->sc; in elink_check_lfa()
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
73 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
74 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received
75 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync …
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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