Searched +full:rtc32k +full:- +full:clock (Results 1 – 8 of 8) sorted by relevance
/linux/Documentation/devicetree/bindings/clock/ |
H A D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ST-Ericsson DB8500 (U8500) clocks 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 - Linus Walleij <linus.walleij@linaro.org> 14 DB8500 digital baseband system-on-chip and its siblings such as 16 itself, not off-chip clocks. There are four different on-chip 17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and [all …]
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/linux/arch/arm/boot/dts/amlogic/ |
H A D | meson8b-ec100.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 22 stdout-path = "serial0:115200n8"; 30 emmc_pwrseq: emmc-pwrseq { 31 compatible = "mmc-pwrseq-emmc"; 32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; 35 gpio-keys { 36 compatible = "gpio-keys-polled"; [all …]
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/linux/drivers/clk/ux500/ |
H A D | u8500_of_clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Clock definitions for u8500 platform. 5 * Copyright (C) 2012 ST-Ericsson SA 11 #include <linux/clk-provider.h> 12 #include <linux/mfd/dbx500-prcmu.h> 16 #include "reset-prcc.h" 35 if (clkspec->args_count != 2) in ux500_twocell_get() 36 return ERR_PTR(-EINVAL); in ux500_twocell_get() 38 base = clkspec->args[0]; in ux500_twocell_get() 39 bit = clkspec->args[1]; in ux500_twocell_get() [all …]
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/linux/arch/arm/boot/dts/mediatek/ |
H A D | mt7623.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2017-2018 MediaTek Inc. 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/clock/mt2701-clk.h> 13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h> 14 #include <dt-bindings/power/mt2701-power.h> 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/phy/phy.h> 17 #include <dt-bindings/reset/mt2701-resets.h> [all …]
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H A D | mt2701.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/clock/mt2701-clk.h> 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/power/mt2701-power.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/memory/mt2701-larb-port.h> 14 #include <dt-bindings/reset/mt2701-resets.h> 15 #include "mt2701-pinfunc.h" 18 #address-cells = <2>; [all …]
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/linux/drivers/clk/mediatek/ |
H A D | clk-mt8135.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 #include <dt-bindings/clock/mt8135-clk.h> 16 #include "clk-gate.h" 17 #include "clk-mtk.h" 18 #include "clk-pll.h" 251 "rtc32k", 548 { .compatible = "mediatek,mt8135-infracfg", .data = &infra_desc }, 549 { .compatible = "mediatek,mt8135-pericfg", .data = &peri_desc }, 550 { .compatible = "mediatek,mt8135-topckgen", .data = &topck_desc }, 557 .name = "clk-mt8135",
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H A D | clk-mt2701.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 11 #include "clk-cpumux.h" 12 #include "clk-gate.h" 13 #include "clk-mtk.h" 14 #include "clk-pll.h" 16 #include <dt-bindings/clock/mt2701-clk.h> 139 FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1), 663 struct device_node *node = pdev->dev.of_node; in mtk_topckgen_init() 671 return -ENOMEM; in mtk_topckgen_init() [all …]
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/linux/arch/arm/boot/dts/st/ |
H A D | ste-dbx5x0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <dt-bindings/interrupt-controller/irq.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/clock/ste-db8500-clkout.h> 9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> 10 #include <dt-bindings/mfd/dbx500-prcmu.h> 11 #include <dt-bindings/arm/ux500_pm_domains.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/thermal/thermal.h> 16 #address-cells = <1>; [all …]
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