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/freebsd/sys/amd64/vmm/io/
H A Dvrtc.c45 #include <isa/rtc.h>
53 /* Register layout of the RTC */
80 u_int addr; /* RTC register to read or write */
91 * RTC time is considered "broken" if:
92 * - RTC updates are halted by the guest
93 * - RTC date/time fields have invalid values
108 static MALLOC_DEFINE(M_VRTC, "vrtc", "bhyve virtual rtc");
116 &rtc_flag_broken_time, 0, "Stop guest when invalid RTC time is detected");
122 * The RTC is counting only when dividers are not held in reset. in divider_enabled()
131 * RTC date/time can be updated only if: in update_enabled()
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/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dallwinner,sun6i-a31-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
7 title: Allwinner A31 RTC
20 - allwinner,sun6i-a31-rtc
21 - allwinner,sun8i-a23-rtc
22 - allwinner,sun8i-h3-rtc
23 - allwinner,sun8i-r40-rtc
24 - allwinner,sun8i-v3-rtc
25 - allwinner,sun50i-h5-rtc
26 - allwinner,sun50i-h6-rtc
27 - allwinner,sun50i-h616-rtc
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H A Dingenic,rtc.yaml4 $id: http://devicetree.org/schemas/rtc/ingenic,rtc.yaml#
13 - $ref: rtc.yaml#
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
30 - ingenic,jz4740-rtc
31 - ingenic,jz4760-rtc
33 - const: ingenic,jz4725b-rtc
34 - const: ingenic,jz4740-rtc
37 - ingenic,jz4770-rtc
38 - ingenic,jz4780-rtc
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H A Ds3c-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/s3c-rtc.yaml#
16 - samsung,s3c2410-rtc
17 - samsung,s3c2416-rtc
18 - samsung,s3c2443-rtc
19 - samsung,s3c6410-rtc
22 - samsung,exynos7-rtc
23 - samsung,exynos850-rtc
24 - const: samsung,s3c6410-rtc
25 - const: samsung,exynos3250-rtc
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H A Dst,stm32-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
18 - st,stm32mp25-rtc
44 domain (RTC registers) write protection.
57 "^rtc-[a-z]+-[0-9]+$":
61 Configuration of STM32 RTC pins description. STM32 RTC is able to output
64 - Alarm out that allow to send a pulse on a pin when alarm A of the RTC
83 const: st,stm32-rtc
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H A Dmoxa,moxart-rtc.txt5 - compatible : Should be "moxa,moxart-rtc"
6 - rtc-sclk-gpios : RTC sclk gpio, with zero flags
7 - rtc-data-gpios : RTC data gpio, with zero flags
8 - rtc-reset-gpios : RTC reset gpio, with zero flags
12 rtc: rtc {
13 compatible = "moxa,moxart-rtc";
14 rtc-sclk-gpios = <&gpio 5 0>;
15 rtc-data-gpios = <&gpio 6 0>;
16 rtc-reset-gpios = <&gpio 7 0>;
H A Dnvidia,tegra20-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
14 The Tegra RTC maintains seconds and milliseconds counters, and five
21 - const: nvidia,tegra20-rtc
24 - nvidia,tegra30-rtc
25 - nvidia,tegra114-rtc
26 - nvidia,tegra124-rtc
27 - nvidia,tegra210-rtc
28 - nvidia,tegra186-rtc
29 - nvidia,tegra194-rtc
30 - nvidia,tegra234-rtc
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H A Dtrivial-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
13 This is a list of trivial RTC devices that have simple device tree
18 - $ref: rtc.yaml#
28 - aspeed,ast2400-rtc
30 - aspeed,ast2500-rtc
32 - aspeed,ast2600-rtc
34 - cnxt,cx92755-rtc
35 # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
39 # Extremely Accurate I²C RTC with Integrated Crystal and SRAM
43 # EM Microelectronic EM3027 RTC
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H A Dloongson,rtc.yaml4 $id: http://devicetree.org/schemas/rtc/loongson,rtc.yaml#
11 counter) as the RTC.
17 - $ref: rtc.yaml#
23 - loongson,ls1b-rtc
24 - loongson,ls1c-rtc
25 - loongson,ls7a-rtc
26 - loongson,ls2k1000-rtc
29 - loongson,ls2k2000-rtc
30 - loongson,ls2k0500-rtc
31 - const: loongson,ls7a-rtc
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H A Dmarvell,armada-380-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
7 title: RTC controller for the Armada 38x, 7K and 8K SoCs
13 - $ref: rtc.yaml#
18 - marvell,armada-380-rtc
19 - marvell,armada-8k-rtc
23 - description: RTC base address size
28 - const: rtc
29 - const: rtc-soc
46 rtc@a3800 {
47 compatible = "marvell,armada-380-rtc";
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H A Dxlnx,zynqmp-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
11 The RTC controller has separate IRQ lines for seconds and alarm.
17 - $ref: rtc.yaml#
22 - const: xlnx,zynqmp-rtc
25 - xlnx,versal-rtc
26 - xlnx,versal-net-rtc
27 - const: xlnx,zynqmp-rtc
37 - const: rtc
74 rtc: rtc@ffa60000 {
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H A Dqcom-pm8xxx-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rtc.yaml#
7 title: Qualcomm PM8xxx PMIC RTC device
16 - qcom,pm8058-rtc
17 - qcom,pm8921-rtc
18 - qcom,pm8941-rtc
19 - qcom,pmk8350-rtc
22 - qcom,pm8018-rtc
23 - const: qcom,pm8921-rtc
32 - const: rtc
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H A Datmel,at91rm9200-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/atmel,at91rm9200-rtc.yaml#
7 title: Atmel AT91 RTC
10 - $ref: rtc.yaml#
19 - atmel,at91rm9200-rtc
20 - atmel,at91sam9x5-rtc
21 - atmel,sama5d4-rtc
22 - atmel,sama5d2-rtc
23 - microchip,sam9x60-rtc
24 - microchip,sama7g5-rtc
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H A Drtc-omap.txt5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
35 rtc@1c23000 {
36 compatible = "ti,da830-rtc";
H A Dsa1100-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/sa1100-rtc.yaml#
10 - $ref: rtc.yaml#
20 - mrvl,sa1100-rtc
21 - mrvl,mmp-rtc
37 - const: rtc 1Hz
38 - const: rtc alarm
50 rtc: rtc@d4010000 {
51 compatible = "mrvl,mmp-rtc";
54 interrupt-names = "rtc 1Hz", "rtc alarm";
H A Darmada-380-rtc.txt3 RTC controller for the Armada 38x, 7K and 8K SoCs
7 "marvell,armada-380-rtc" for Armada 38x SoC
8 "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
12 * "rtc" for the RTC registers
13 * "rtc-soc" for the SoC related registers and among them the one
15 - interrupts: IRQ line for the RTC.
19 rtc@a3800 {
20 compatible = "marvell,armada-380-rtc";
22 reg-names = "rtc", "rtc-soc";
H A Dmediatek,mt7622-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml#
7 title: MediaTek MT7622 on-SoC RTC
10 - $ref: rtc.yaml#
18 - const: mediatek,mt7622-rtc
19 - const: mediatek,soc-rtc
31 const: rtc
46 rtc@10212800 {
47 compatible = "mediatek,mt7622-rtc", "mediatek,soc-rtc";
51 clock-names = "rtc";
H A Drtc-mt7622.txt1 Device-Tree bindings for MediaTek SoC based RTC
5 "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
7 - interrupts : Should contain the interrupt for RTC alarm;
10 - clock-names : Should contain "rtc" entries
14 rtc: rtc@10212800 {
15 compatible = "mediatek,mt7622-rtc",
16 "mediatek,soc-rtc";
20 clock-names = "rtc";
H A Drtc-mt6397.txt1 Device-Tree bindings for MediaTek PMIC based RTC
3 MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
4 as a type of multi-function device (MFD). The RTC can be configured and set up
16 "mediatek,mt6323-rtc": for MT6323 PMIC
17 "mediatek,mt6358-rtc": for MT6358 PMIC
18 "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
19 "mediatek,mt6397-rtc": for MT6397 PMIC
28 rtc {
29 compatible = "mediatek,mt6323-rtc";
H A Damlogic,meson6-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/amlogic,meson6-rtc.yaml#
7 title: Amlogic Meson6, Meson8, Meson8b and Meson8m2 RTC
14 - $ref: rtc.yaml#
21 - amlogic,meson6-rtc
22 - amlogic,meson8-rtc
23 - amlogic,meson8b-rtc
24 - amlogic,meson8m2-rtc
50 rtc: rtc
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H A Dmicrochip,mfps-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
20 - microchip,mpfs-rtc
31 to that of the RTC's count register.
39 strobe (typically 1 Hz) for the calendar counter. By default, the rtc
45 - const: rtc
60 rtc@20124000 {
61 compatible = "microchip,mpfs-rtc";
64 clock-names = "rtc", "rtcref";
H A Drtc-meson.txt1 * Amlogic Meson6, Meson8, Meson8b and Meson8m2 RTC
5 * "amlogic,meson6-rtc"
6 * "amlogic,meson8-rtc"
7 * "amlogic,meson8b-rtc"
8 * "amlogic,meson8m2-rtc"
11 - interrupts: the interrupt line of the RTC block.
13 - vdd-supply: reference to the power supply of the RTC block.
25 rtc: rtc@740 {
26 compatible = "amlogic,meson6-rtc";
H A Dnxp,lpc1788-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/nxp,lpc1788-rtc.yaml#
10 The LPC1788 RTC provides calendar and clock functionality
17 - $ref: rtc.yaml#
21 const: nxp,lpc1788-rtc
28 - description: RTC clock
33 - const: rtc
52 rtc@40046000 {
53 compatible = "nxp,lpc1788-rtc";
56 clock-names = "rtc", "reg";
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_rtc.h38 /* FM RTC Registers definitions */
77 @Description FM RTC Alarm Polarity Options.
85 @Description FM RTC Trigger Polarity Options.
93 @Description IEEE1588 Timer Module FM RTC Optional Clock Sources.
99 E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */
102 /* RTC default values */
115 @Description FM RTC timer alarm
123 @Description FM RTC timer Ex trigger
172 * fman_rtc_defconfig() - Get default RTC configuration
176 * initializing RTC. The user can overwrite any of the values before calling
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/freebsd/sys/kern/
H A Dsubr_rtc.c78 "Enable debug printing of RTC clock I/O; 1=reads, 2=writes, 3=both.");
83 "Trigger one-time IO on RTC clocks; 1=read (and discard), 2=write");
126 SX_SYSINIT(rtc_list_lock_init, &rtc_list_lock, "rtc list");
137 struct rtc_instance *rtc; in settime_task_func() local
140 rtc = arg; in settime_task_func()
141 if (!(rtc->flags & CLOCKF_SETTIME_NO_TS)) { in settime_task_func()
143 if (!(rtc->flags & CLOCKF_SETTIME_NO_ADJ)) { in settime_task_func()
145 timespecadd(&ts, &rtc->resadj, &ts); in settime_task_func()
151 error = CLOCK_SETTIME(rtc->clockdev, &ts); in settime_task_func()
153 device_printf(rtc->clockdev, "CLOCK_SETTIME error %d\n", error); in settime_task_func()
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