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/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dallwinner,sun6i-a31-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 RTC
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#clock-cells":
19 - enum:
20 - allwinner,sun6i-a31-rtc
[all …]
H A Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/ingenic,rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
14 - if:
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
[all …]
H A Ds3c-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/s3c-rtc.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dst,stm32-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
18 - st,stm32mp25-rtc
27 clock-names:
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H A Dmoxa,moxart-rtc.txt1 MOXA ART real-time clock
5 - compatible : Should be "moxa,moxart-rtc"
6 - rtc-sclk-gpios : RTC sclk gpio, with zero flags
7 - rtc-data-gpios : RTC data gpio, with zero flags
8 - rtc-reset-gpios : RTC reset gpio, with zero flags
12 rtc: rtc {
13 compatible = "moxa,moxart-rtc";
14 rtc-sclk-gpios = <&gpio 5 0>;
15 rtc-data-gpios = <&gpio 6 0>;
16 rtc-reset-gpios = <&gpio 7 0>;
H A Dnvidia,tegra20-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra real-time clock
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra RTC maintains seconds and milliseconds counters, and five
16 from low-power state.
21 - const: nvidia,tegra20-rtc
[all …]
H A Dtrivial-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 This is a list of trivial RTC devices that have simple device tree
18 - $ref: rtc.yaml#
23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
24 - abracon,abb5zes3
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
[all …]
H A Dloongson,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/loongson,rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson Real-Time Clock
10 The Loongson family chips use an on-chip counter 0 (Time Of Year
11 counter) as the RTC.
14 - Binbin Zhou <zhoubinbin@loongson.cn>
17 - $ref: rtc.yaml#
22 - enum:
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H A Dmarvell,armada-380-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RTC controller for the Armada 38x, 7K and 8K SoCs
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
13 - $ref: rtc.yaml#
18 - marvell,armada-380-rtc
19 - marvell,armada-8k-rtc
23 - description: RTC base address size
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H A Dxlnx,zynqmp-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
11 The RTC controller has separate IRQ lines for seconds and alarm.
14 - Michal Simek <michal.simek@amd.com>
17 - $ref: rtc.yaml#
22 - const: xlnx,zynqmp-rtc
23 - items:
[all …]
H A Dqcom-pm8xxx-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/qcom-pm8xx
[all...]
H A Drtc-omap.txt4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
[all …]
H A Datmel,at91rm9200-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/atmel,at91rm9200-rtc.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dsa1100-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/rtc/sa1100-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: rtc.yaml#
13 - Alessandro Zummo <a.zummo@towertech.it>
14 - Alexandre Belloni <alexandre.belloni@bootlin.com>
15 - Rob Herring <robh@kernel.org>
20 - mrvl,sa1100-rtc
21 - mrvl,mmp-rtc
[all …]
H A Darmada-380-rtc.txt3 RTC controller for the Armada 38x, 7K and 8K SoCs
6 - compatible : Should be one of the following:
7 "marvell,armada-380-rtc" for Armada 38x SoC
8 "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
9 - reg: a list of base address and size pairs, one for each entry in
10 reg-names
11 - reg names: should contain:
12 * "rtc" for the RTC registers
13 * "rtc-soc" for the SoC related registers and among them the one
15 - interrupts: IRQ line for the RTC.
[all …]
H A Dmediatek,mt7622-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7622 on-SoC RTC
10 - $ref: rtc.yaml#
13 - Sean Wang <sean.wang@mediatek.com>
18 - const: mediatek,mt7622-rtc
19 - const: mediatek,soc-rtc
30 clock-names:
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H A Drtc-mt7622.txt1 Device-Tree bindings for MediaTek SoC based RTC
4 - compatible : Should be
5 "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
6 - reg : Specifies base physical address and size of the registers;
7 - interrupts : Should contain the interrupt for RTC alarm;
8 - clocks : Specifies list of clock specifiers, corresponding to
9 entries in clock-names property;
10 - clock-names : Should contain "rtc" entries
14 rtc: rtc@10212800 {
15 compatible = "mediatek,mt7622-rtc",
[all …]
H A Damlogic,meson6-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/amlogi
[all...]
H A Dmicrochip,mfps-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
15 - Lewis Hanly <lewis.hanly@microchip.com>
20 - microchip,mpfs-rtc
27 - description: |
[all …]
H A Drtc-mt6397.txt1 Device-Tree bindings for MediaTek PMIC based RTC
3 MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
4 as a type of multi-function device (MFD). The RTC can be configured and set up
15 - compatible: Should be one of follows
16 "mediatek,mt6323-rtc": for MT6323 PMIC
17 "mediatek,mt6358-rtc": for MT6358 PMIC
18 "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
19 "mediatek,mt6397-rtc": for MT6397 PMIC
28 rtc {
29 compatible = "mediatek,mt6323-rtc";
H A Dnxp,lpc1788-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/nxp,lpc1788-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP LPC1788 real-time clock
10 The LPC1788 RTC provides calendar and clock functionality
14 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
17 - $ref: rtc.yaml#
21 const: nxp,lpc1788-rtc
28 - description: RTC clock
[all …]
H A Dfsl,stmp3xxx-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/fsl,stmp3xxx-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
13 - $ref: rtc.yaml#
18 - items:
19 - enum:
20 - fsl,imx28-rtc
21 - fsl,imx23-rtc
[all …]
/freebsd/sys/amd64/vmm/io/
H A Dvrtc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <isa/rtc.h>
53 /* Register layout of the RTC */
71 uint8_t nvram2[128 - 51];
80 u_int addr; /* RTC register to read or write */
86 #define VRTC_LOCK(vrtc) mtx_lock(&((vrtc)->mtx))
87 #define VRTC_UNLOCK(vrtc) mtx_unlock(&((vrtc)->mtx))
88 #define VRTC_LOCKED(vrtc) mtx_owned(&((vrtc)->mtx))
91 * RTC time is considered "broken" if:
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/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_rtc.h38 /* FM RTC Registers definitions */
77 @Description FM RTC Alarm Polarity Options.
80 E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH, /**< Active-high output polarity */
81 E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW /**< Active-low output polarity */
85 @Description FM RTC Trigger Polarity Options.
93 @Description IEEE1588 Timer Module FM RTC Optional Clock Sources.
99 E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */
102 /* RTC default values */
115 @Description FM RTC timer alarm
123 @Description FM RTC timer Ex trigger
[all …]
/freebsd/sys/kern/
H A Dsubr_rtc.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
48 * Helpers for time-of-day clocks. This is useful for architectures that need
50 * code more machine-independent.
78 "Enable debug printing of RTC clock I/O; 1=reads, 2=writes, 3=both.");
83 "Trigger one-time IO on RTC clocks; 1=read (and discard), 2=write");
88 0, "Disallow adjusting time-of-day clock");
95 * the clock's resolution, which is useful mainly on clocks with a whole-second
126 SX_SYSINIT(rtc_list_lock_init, &rtc_list_lock, "rtc list");
137 struct rtc_instance *rtc; in settime_task_func() local
[all …]

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