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/linux/Documentation/devicetree/bindings/reset/
H A Dhisilicon,hi3660-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
15 The reset controller registers are part of the system-ctl block on
21 - items:
22 - const: hisilicon,hi3660-reset
23 - items:
24 - const: hisilicon,hi3670-reset
[all …]
H A Dmicrochip,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
25 - microchip,lan966x-switch-reset
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H A Dimg,pistachio-reset.txt18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
29 #clock-cells = <1>;
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
47 spdif_out: spdif-out@18100d00 {
50 reset-names = "rst";
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/linux/drivers/reset/hisilicon/
H A Dreset-hi3660.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2016-2017 Linaro Ltd.
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 #include <linux/mfd/syscon.h>
12 #include <linux/reset-controller.h>
15 struct reset_controller_dev rst; member
20 container_of(_rst, struct hi3660_reset_controller, rst)
30 return regmap_write(rc->map, offset, mask); in hi3660_reset_program_hw()
32 return regmap_write(rc->map, offset + 4, mask); in hi3660_reset_program_hw()
70 offset = reset_spec->args[0]; in hi3660_reset_xlate()
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux/drivers/iio/adc/
H A Daspeed_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/clk-provider.h>
29 #include <linux/mfd/syscon.h>
116 struct reset_control *rst; member
177 struct device_node *syscon; in aspeed_adc_set_trim_data() local
182 syscon = of_find_node_by_name(NULL, "syscon"); in aspeed_adc_set_trim_data()
183 if (syscon == NULL) { in aspeed_adc_set_trim_data()
184 dev_warn(data->dev, "Couldn't find syscon node\n"); in aspeed_adc_set_trim_data()
185 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
187 scu = syscon_node_to_regmap(syscon); in aspeed_adc_set_trim_data()
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/linux/Documentation/devicetree/bindings/net/
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
27 - items:
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H A Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
/linux/drivers/phy/socionext/
H A Dphy-uniphier-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
12 #include <linux/mfd/syscon.h>
63 struct reset_control *rst, *rst_gio; member
80 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()
81 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
82 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
87 u32 val = readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_read()
126 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
129 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
/linux/drivers/clk/visconti/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/mfd/syscon.h>
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
27 u32 rst = BIT(data->rs_idx); in visconti_reset_assert() local
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
42 u32 rst = BIT(data->rs_idx); in visconti_reset_deassert() local
46 spin_lock_irqsave(reset->lock, flags); in visconti_reset_deassert()
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
[all …]
/linux/drivers/reset/sti/
H A Dreset-syscfg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Inspired by mach-imx/src.c
16 #include <linux/mfd/syscon.h>
18 #include "reset-syscfg.h"
21 * struct syscfg_reset_channel - Reset channel regmap configuration
32 * struct syscfg_reset_controller - A reset controller which groups together
36 * @rst: base reset controller structure.
42 struct reset_controller_dev rst; member
48 container_of(_rst, struct syscfg_reset_controller, rst)
53 struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev); in syscfg_reset_program_hw() local
[all …]
/linux/Documentation/devicetree/bindings/
H A Dwriting-bindings.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Documentation/devicetree/bindings/submitting-patches.rst
17 - DO attempt to make bindings complete even if a driver doesn't support some
21 - DON'T refer to Linux or "device driver" in bindings. Bindings should be
24 - DO use node names matching the class of the device. Many standard names are
27 - DO check that the example matches the documentation especially after making
30 - DON'T create nodes just for the sake of instantiating drivers. Multi-function
34 - DON'T use 'syscon' alone without a specific compatible string. A 'syscon'
42 - DO make 'compatible' properties specific. DON'T use wildcards in compatible
47 - DO use a vendor prefix on device-specific property names. Consider if
[all …]
/linux/drivers/reset/
H A Dreset-k210.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/reset-controller.h>
9 #include <linux/mfd/syscon.h>
11 #include <soc/canaan/k210-sysctl.h>
13 #include <dt-bindings/reset/k210-rst.h>
33 return regmap_update_bits(ksr->map, K210_SYSCTL_PERI_RESET, BIT(id), 1); in k210_rst_assert()
41 return regmap_update_bits(ksr->map, K210_SYSCTL_PERI_RESET, BIT(id), 0); in k210_rst_deassert()
65 ret = regmap_read(ksr->map, K210_SYSCTL_PERI_RESET, &reg); in k210_rst_status()
75 unsigned long id = reset_spec->args[0]; in k210_rst_xlate()
78 return -EINVAL; in k210_rst_xlate()
[all …]
/linux/drivers/gpu/drm/aspeed/
H A Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
5 #include <linux/dma-mapping.h>
7 #include <linux/mfd/syscon.h>
94 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
95 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
96 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
115 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
116 drm->mode_config.min_height = 0; in aspeed_gfx_setup_mode_config()
117 drm->mode_config.max_width = 800; in aspeed_gfx_setup_mode_config()
118 drm->mode_config.max_height = 600; in aspeed_gfx_setup_mode_config()
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
[all …]
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/arch/arm64/boot/dts/bitmain/
H A Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
/linux/drivers/watchdog/
H A Dmt7621_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Ralink MT7621/MT7628 built-in hardware watchdog timer
18 #include <linux/mfd/syscon.h>
36 struct reset_control *rst; member
61 rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); in mt7621_wdt_ping()
70 w->timeout = t; in mt7621_wdt_set_timeout()
71 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000); in mt7621_wdt_set_timeout()
83 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); in mt7621_wdt_start()
85 mt7621_wdt_set_timeout(w, w->timeout); in mt7621_wdt_start()
87 t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); in mt7621_wdt_start()
[all …]
/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
6 #include <linux/mfd/syscon.h>
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
[all …]
H A Dclk-ast2600.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
7 #include <linux/mfd/syscon.h>
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
20 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).
94 * handled by using -1 as the index for the reset, and the consumer must
103 /* clk rst name parent flags */
104 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
105 [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
[all …]
/linux/sound/soc/uniphier/
H A Daio-cpu.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (c) 2016-2018 Socionext Inc.
10 #include <linux/mfd/syscon.h>
25 struct device *dev = &chip->pdev->dev; in is_valid_pll()
27 if (pll_id < 0 || chip->num_plls <= pll_id) { in is_valid_pll()
32 return chip->plls[pll_id].enable; in is_valid_pll()
36 * find_volume - find volume supported HW port by HW port number
51 for (i = 0; i < chip->num_aios; i++) { in find_volume()
52 struct uniphier_aio_sub *sub = &chip->aios[i].sub[0]; in find_volume()
54 if (!sub->swm) in find_volume()
[all …]
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
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