/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip SoC Naneng Combo Phy 10 - Heiko Stuebner <heiko@sntech.de> 15 - rockchip,rk3568-naneng-combphy 16 - rockchip,rk3588-naneng-combphy 23 - description: reference clock 24 - description: apb clock [all …]
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H A D | rockchip-pcie-phy.txt | 1 Rockchip PCIE PHY 2 ----------------------- 5 - compatible: rockchip,rk3399-pcie-phy 6 - clocks: Must contain an entry in clock-names. 7 See ../clocks/clock-bindings.txt for details. 8 - clock-names: Must be "refclk" 9 - resets: Must contain an entry in reset-names. 11 - reset-names: Must be "phy" 13 Required properties for legacy PHY mode (deprecated): 14 - #phy-cells: must be 0 [all …]
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H A D | rockchip,pcie3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip PCIe v3 phy 10 - Heiko Stuebner <heiko@sntech.de> 15 - rockchip,rk3568-pcie3-phy 16 - rockchip,rk3588-pcie3-phy 25 clock-names: 29 data-lanes: [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
H A D | rk3588-extra.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 6 #include "rk3588-base.dtsi" 7 #include "rk3588-extra-pinctrl.dtsi" 11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 16 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 19 phy-names = "usb2-phy", "usb3-phy"; 21 power-domains = <&power RK3588_PD_USB>; 24 snps,dis-u2-freeclk-exists-quirk; 25 snps,dis-del-phy-power-chg-quirk; [all …]
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H A D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 9 compatible = "rockchip,rk3568"; 12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 16 clock-names = "sata", "pmalive", "rxoob"; 19 phy-names = "sata-phy"; 20 ports-implemented = <0x1>; 21 power-domains = <&power RK3568_PD_PIPE>; 26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 31 compatible = "rockchip,rk3568-qos", "syscon"; [all …]
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H A D | rk3568-lubancat-2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 8 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/pinctrl/rockchip.h> 12 #include <dt-bindings/soc/rockchip,vop2.h> 17 compatible = "embedfire,lubancat-2", "rockchip,rk3568"; 27 stdout-path = "serial2:1500000n8"; 31 compatible = "gpio-leds"; [all …]
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H A D | rk3399-base.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 6 #include <dt-bindings/clock/rk3399-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3399-power.h> 12 #include <dt-bindings/thermal/thermal.h> 15 compatible = "rockchip,rk3399"; [all …]
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H A D | rk3568-rock-3a.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 4 #include <dt-bindings/gpio/gpio.h> 5 #include <dt-bindings/leds/common.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/soc/rockchip,vop2.h> 12 compatible = "radxa,rock3a", "rockchip,rk3568"; 22 stdout-path = "serial2:1500000n8"; 25 hdmi-con { 26 compatible = "hdmi-connector"; [all …]
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H A D | rk3568-roc-pc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 6 /dts-v1/; 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/soc/rockchip,vop2.h> 15 compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568"; 25 stdout-path = "serial2:1500000n8"; 28 dc_12v: dc-12v-regulator { 29 compatible = "regulator-fixed"; [all …]
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H A D | rk3568-odroid-m1.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/soc/rockchip,vop2.h> 15 model = "Hardkernel ODROID-M1"; 16 compatible = "hardkernel,odroid-m1", "rockchip,rk3568"; 29 stdout-path = "serial2:1500000n8"; 32 dc_12v: dc-12v-regulator { [all …]
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H A D | rk3566-rock-3c.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 4 #include <dt-bindings/gpio/gpio.h> 5 #include <dt-bindings/leds/common.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/soc/rockchip,vop2.h> 12 compatible = "radxa,rock-3c", "rockchip,rk3566"; 22 stdout-path = "serial2:1500000n8"; 25 gmac1_clkin: external-gmac1-clock { 26 compatible = "fixed-clock"; [all …]
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H A D | rk3399-ficus.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 9 /dts-v1/; 10 #include "rk3399-rock960.dtsi" 14 compatible = "vamrs,ficus", "rockchip,rk3399"; 21 stdout-path = "serial2:1500000n8"; 24 clkin_gmac: external-gmac-cloc [all...] |
H A D | rk3568-radxa-e25.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 4 #include "rk3568-radxa-cm3i.dtsi" 8 compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; 14 pwm-leds { 15 compatible = "pwm-leds-multicolor"; 17 multi-led { 19 max-brightness = <255>; 21 led-red { 26 led-green { [all …]
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H A D | rk3566-roc-pc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/soc/rockchip,vop2.h> 12 compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566"; 22 stdout-path = "serial2:1500000n8"; 25 gmac1_clkin: external-gmac1-clock { 26 compatible = "fixed-clock"; 27 clock-frequency = <125000000>; [all …]
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H A D | rk3566-quartz64-a.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/soc/rockchip,vop2.h> 12 compatible = "pine64,quartz64-a", "rockchip,rk3566"; 21 stdout-path = "serial2:1500000n8"; 24 gmac1_clkin: external-gmac1-clock { 25 compatible = "fixed-clock"; 26 clock-frequency = <125000000>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pci/ |
H A D | rockchip-pcie-ep.txt | 1 * Rockchip AXI PCIe Endpoint Controller DT description 4 - compatible: Should contain "rockchip,rk3399-pcie-ep" 5 - reg: Two register ranges as listed in the reg-names property 6 - reg-names: Must include the following names 7 - "apb-base" 8 - "mem-base" 9 - clocks: Must contain an entry for each entry in clock-names. 10 See ../clocks/clock-bindings.txt for details. 11 - clock-names: Must include the following entries: 12 - "aclk" [all …]
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H A D | rockchip,rk3399-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip AXI PCIe Endpoint 10 - Shawn Lin <shawn.lin@rock-chips.com> 13 - $ref: /schemas/pci/pci-ep.yaml# 14 - $ref: rockchip,rk3399-pcie-common.yaml# 18 const: rockchip,rk3399-pcie-ep 22 reg-names: [all …]
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H A D | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description 4 - #address-cells: Address representation for root ports, set to <3> 5 - #size-cells: Size representation for root ports, set to <2> 6 - #interrupt-cells: specifies the number of cells needed to encode an 8 - compatible: Should contain "rockchip,rk3399-pcie" 9 - reg: Two register ranges as listed in the reg-names property 10 - reg-names: Must include the following names 11 - "axi-base" 12 - "apb-base" 13 - clocks: Must contain an entry for each entry in clock-names. [all …]
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H A D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip AXI PCIe Root Port Bridge Host 10 - Shawn Lin <shawn.lin@rock-chips.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 14 - $ref: rockchip,rk3399-pcie-common.yaml# 18 const: rockchip,rk3399-pcie 22 reg-names: [all …]
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H A D | rockchip-dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: DesignWare based PCIe Endpoint controller on Rockchip SoCs 10 - Niklas Cassel <cassel@kernel.org> 13 RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare 14 PCIe IP and thus inherits all the common properties defined in 15 snps,dw-pcie-ep.yaml. 18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# [all …]
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H A D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs 10 - Shawn Lin <shawn.lin@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com> 12 - Heiko Stuebner <heiko@sntech.de> 15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare 16 PCIe IP and thus inherits all the common properties defined in [all …]
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H A D | rockchip,rk3399-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip AXI PCIe Bridge Common Properties 10 - Shawn Lin <shawn.lin@rock-chips.com> 19 clock-names: 21 - const: aclk 22 - const: aclk-perf 23 - const: hclk [all …]
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H A D | rockchip-dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: DesignWare based PCIe RC/EP controller on Rockchip SoCs 10 - Shawn Lin <shawn.lin@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com> 12 - Heiko Stuebner <heiko@sntech.de> 15 Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip 22 - description: AHB clock for PCIe master [all …]
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/freebsd/sys/contrib/device-tree/Bindings/soc/rockchip/ |
H A D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip General Register Files (GRF) 10 - Heiko Stuebner <heiko@sntech.de> 15 - items: 16 - enum: 17 - rockchip,rk3288-sgrf 18 - rockchip,rk3566-pipe-grf [all …]
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/freebsd/sys/contrib/device-tree/Bindings/mfd/ |
H A D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 12 represent as any specific type of device. The typical use-case is 13 for some other node's driver, or platform-specific code, to acquire 20 - Lee Jones <lee@kernel.org> 30 - al,alpine-sysfabric-servic 31 - allwinner,sun8i-a83t-system-controller 32 - allwinner,sun8i-h3-system-controller 33 - allwinner,sun8i-v3s-system-controller [all …]
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