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/linux/sound/soc/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "ASoC support for Rockchip"
7 the Rockchip SoCs' Audio interfaces. You will also need to
11 tristate "Rockchip I2S Device Driver"
16 Rockchip I2S device. The device supports up to maximum of
20 tristate "Rockchip I2S/TDM Device Driver"
25 Rockchip I2S/TDM devices, found in Rockchip SoCs. These devices
31 tristate "Rockchip PDM Controller Driver"
37 Rockchip PDM Controller. The Controller supports up to maximum of
41 tristate "Rockchip SPDIF Device Driver"
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H A Drockchip_spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rk_spdif.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
33 struct device *dev;
44 { .compatible = "rockchip,rk3066-spdif",
46 { .compatible = "rockchip,rk3188-spdif",
48 { .compatible = "rockchip,rk3228-spdif",
50 { .compatible = "rockchip,rk3288-spdif",
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H A Drockchip_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
24 #define DRV_NAME "rockchip-i2s"
32 struct device *dev;
66 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on)) in i2s_pinctrl_select_bclk_on()
67 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on); in i2s_pinctrl_select_bclk_on()
70 dev_err(i2s->dev, "bclk enable failed %d\n", ret); in i2s_pinctrl_select_bclk_on()
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H A Drockchip_max98090.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip machine ASoC driver for boards using a MAX90809 CODEC.
5 * Copyright (c) 2014, ROCKCHIP CORPORATION. All rights reserved.
21 #define DRV_NAME "rockchip-snd-max98090"
111 struct snd_soc_dapm_context *dapm = &jack->card->dapm; in rk_jack_event()
167 return -EINVAL; in rk_aif1_hw_params()
173 dev_err(cpu_dai->dev, "Can't set cpu dai clock %d\n", ret); in rk_aif1_hw_params()
181 if (!strcmp(rtd->dai_link->name, "HDMI")) in rk_aif1_hw_params()
185 dev_err(codec_dai->dev, "Can't set codec dai clock %d\n", ret); in rk_aif1_hw_params()
198 return snd_pcm_hw_constraint_minmax(substream->runtime, in rk_aif1_startup()
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H A Drockchip_pdm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
31 struct device *dev;
91 if ((div & (div - 1)) == 0) { in get_pdm_clk()
93 rate = clk_round_rate(pdm->clk, clkref[i].clk); in get_pdm_clk()
103 clk = clk_round_rate(pdm->clk, PDM_SIGNOFF_CLK_RATE); in get_pdm_clk()
182 regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, in rockchip_pdm_rxctrl()
184 regmap_update_bits(pdm->regmap, PDM_SYSCONFIG, in rockchip_pdm_rxctrl()
187 regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, in rockchip_pdm_rxctrl()
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/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PWM controller
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-drm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DRM master device
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The Rockchip DRM master device is a virtual device needed to list all
20 const: rockchip,display-subsystem
23 $ref: /schemas/types.yaml#/definitions/phandle-array
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/linux/arch/arm/mach-rockchip/
H A Drockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Device Tree support for Rockchip SoCs
24 if (of_machine_is_compatible("rockchip,rk3288")) { in rockchip_timer_init()
41 pr_err("rockchip: could not map timer7 registers\n"); in rockchip_timer_init()
55 "rockchip,rk2928",
56 "rockchip,rk3066a",
57 "rockchip,rk3066b",
58 "rockchip,rk3188",
59 "rockchip,rk3228",
60 "rockchip,rk3288",
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/linux/Documentation/devicetree/bindings/sound/
H A Drockchip-max98090.txt1 ROCKCHIP with MAX98090 CODEC
4 - compatible: "rockchip,rockchip-audio-max98090"
5 - rockchip,model: The user-visible name of this sound complex
6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
10 - rockchip,audio-codec: The phandle of the MAX98090 audio codec.
11 - rockchip,headset-codec: The phandle of Ext chip for jack detection. This is
12 required if there is rockchip,audio-codec.
13 - rockchip,hdmi-codec: The phandle of HDMI device for HDMI codec.
17 /* For max98090-only board. */
19 compatible = "rockchip,rockchip-audio-max98090";
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/linux/drivers/devfreq/
H A Drk3399_dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
12 #include <linux/devfreq-event.h>
24 #include <soc/rockchip/pm_domains.h>
25 #include <soc/rockchip/rockchip_grf.h>
26 #include <soc/rockchip/rk3399_grf.h>
27 #include <soc/rockchip/rockchip_sip.h>
41 struct device *dev;
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3368";
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H A Drk3399-khadas-edge.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pwm/pwm.h>
21 stdout-path = "serial2:1500000n8";
24 clkin_gmac: external-gmac-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
27 clock-output-names = "clkin_gmac";
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/linux/drivers/mfd/
H A Drk8xx-i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip RK805/RK808/RK816/RK817/RK818 Core (I2C) driver
5 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
8 * Author: Chris Zhong <zyw@rock-chips.com>
9 * Author: Zhang Qing <zhangqing@rock-chips.com>
24 static bool rk806_is_volatile_reg(struct device *dev, unsigned int reg) in rk806_is_volatile_reg()
35 static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) in rk808_is_volatile_reg()
39 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but in rk808_is_volatile_reg()
41 * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since in rk808_is_volatile_reg()
63 static bool rk816_is_volatile_reg(struct device *dev, unsigned int reg) in rk816_is_volatile_reg()
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3xxx I2C controller
10 This driver interfaces with the native I2C controller present in Rockchip
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
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/linux/drivers/nvmem/
H A Drockchip-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip eFuse Driver
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Caesar Wang <wxt@rock-chips.com>
11 #include <linux/device.h>
14 #include <linux/nvmem-provider.h>
50 struct device *dev;
62 ret = clk_prepare_enable(efuse->clk); in rockchip_rk3288_efuse_read()
64 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_read()
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
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/linux/drivers/gpu/drm/ci/
H A Dtest.yml1 .test-rules:
3 - if: '$FD_FARM == "offline" && $RUNNER_TAG =~ /^google-freedreno-/'
5 - if: '$COLLABORA_FARM == "offline" && $RUNNER_TAG =~ /^mesa-ci-x86-64-lava-/'
7 - !reference [.no_scheduled_pipelines-rules, rules]
8 - when: on_success
10 .lava-test:
12 - .test-rules
16 - rm -rf install
17 - tar -xf artifacts/install.tar
18 - mv install/* artifacts/.
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/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Rockchip Electronics Co., Ltd.
4 * Author:Mark Yao <mark.yao@rock-chips.com>
10 #include <linux/dma-mapping.h>
29 #include <asm/dma-iommu.h>
40 #define DRIVER_NAME "rockchip"
41 #define DRIVER_DESC "RockChip Soc DRM"
48 * Attach a (component) device to the shared drm dma mapping from master drm
49 * device. This is used by the VOPs to map GEM buffers to a common DMA
53 struct device *dev) in rockchip_drm_dma_attach_device()
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/linux/drivers/char/hw_random/
H A Drockchip-rng.c1 // SPDX-License-Identifier: GPL-2.0
3 * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
5 * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
8 * Lin Jinhan <troy.lin@rock-chips.com>
31 * of ~900 (~87.5% of FIPS 140-2 successes).
35 /* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
62 writel((mask << 16) | val, rng->base + TRNG_RNG_CTL); in rk_rng_write_ctl()
71 ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); in rk_rng_init()
73 dev_err((struct device *) rk_rng->rng.priv, in rk_rng_init()
79 writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); in rk_rng_init()
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/linux/Documentation/devicetree/bindings/mfd/
H A Drockchip,rk817.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rockchip,rk817.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
14 Rockchip RK809/RK817 series PMIC. This device consists of an i2c controlled
21 - rockchip,rk809
22 - rockchip,rk817
30 '#clock-cells':
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/linux/Documentation/devicetree/bindings/ata/
H A Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
13 This document defines device tree bindings for the Synopsys DWC
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
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/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PX30 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
19 preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
20 used in device tree sources. Similar macros exist for the reset sources in
24 clock-output-names:
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H A Drockchip,rk3188-cru.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
19 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
20 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
24 clock-output-names:
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H A Drockchip,rk3568-cru.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ROCKCHIP rk3568 Family Clock Control Module
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
19 preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
20 used in device tree sources.
25 - rockchip,rk3568-cru
[all …]

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