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Searched +full:rk3506 +full:- +full:cru (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3506-cru.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3506 Clock and Reset Unit (CRU)
10 - Finley Xiao <finley.xiao@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3506 CRU generates the clock and also implements reset for SoC
19 const: rockchip,rk3506-cru
24 "#clock-cells":
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Drockchip-saradc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/rockchip-saradc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,saradc
16 - const: rockchip,rk3066-tsadc
17 - const: rockchip,rk3399-saradc
18 - const: rockchip,rk3528-saradc
19 - items:
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/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,px30-dsi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
13 "#phy-cells":
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3506-dsi-dphy
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: spi-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rk3036-spi
24 - const: rockchip,rk3066-spi
25 - const: rockchip,rk3228-spi
26 - const: rockchip,rv1108-spi
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/linux/drivers/clk/rockchip/
H A Drst-rk3506.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
9 #include <dt-bindings/reset/rockchip,rk3506-cru.h>
17 /* CRU-->SOFTRST_CON00 */
28 /* CRU-->SOFTRST_CON02 */
33 /* CRU-->SOFTRST_CON03 */
42 /* CRU-->SOFTRST_CON04 */
53 /* CRU-->SOFTRST_CON05 */
65 /* CRU-->SOFTRST_CON06 */
83 /* CRU-->SOFTRST_CON07 */
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H A Dclk-rk3506.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/rockchip,rk3506-cru.h>
25 * - VCO Frequency: 950MHz to 3800MHZ
26 * - Output Frequency: 19MHz to 3800MHZ
27 * - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode)
28 * - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode)
29 * - post1div: 1 to 7
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
25 - const: rockchip,rk3188-i2c
26 - const: rockchip,rk3228-i2c
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