Home
last modified time | relevance | path

Searched +full:rk3399 +full:- +full:power (Results 1 – 25 of 79) sorted by relevance

1234

/freebsd/sys/contrib/device-tree/Bindings/power/
H A Drockchip,power-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Domains
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 Rockchip processors include support for multiple power domains
16 application scenarios to save power.
18 Power domains contained within power-controller node are
[all …]
H A Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
29 should have power or not have power
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
50 - rockchip,rk3188-io-voltage-domain
[all …]
H A Drockchip-io-domain.txt2 -------------------------------------
9 - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
18 - any logic for deciding what voltage we should set regulators to
19 - any logic for deciding whether regulators (or internal SoC blocks)
20 should have power or not have power
33 - compatible: should be one of:
34 - "rockchip,px30-io-voltage-domain" for px30
35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
36 - "rockchip,rk3188-io-voltage-domain" for rk3188
37 - "rockchip,rk3228-io-voltage-domain" for rk3228
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
[all …]
H A Drk3399-sapphire-excavator.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-sapphire.dtsi"
10 model = "Excavator-RK3399 Board";
11 compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
17 adc-keys {
18 compatible = "adc-keys";
19 io-channels = <&saradc 1>;
20 io-channel-names = "buttons";
21 keyup-threshold-microvolt = <1800000>;
[all …]
H A Drk3399-roc-pc-mezzanine.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
19 poe_12v: poe-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "poe_12v";
22 regulator-always-on;
[all …]
H A Drk3399-nanopi-r4s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
15 /dts-v1/;
16 #include "rk3399-nanopi4.dtsi"
20 compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
22 /delete-node/ display-subsystem;
24 gpio-leds {
25 pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
27 /delete-node/ led-0;
29 lan_led: led-lan {
[all …]
H A Drk3399-nanopi-m4b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2020 Chen-Yu Tsai <wens@csie.org>
8 /dts-v1/;
9 #include "rk3399-nanopi-m4.dts"
13 compatible = "friendlyarm,nanopi-m4b", "rockchip,rk3399";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 1>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1500000>;
[all …]
H A Drk3399-gru-scarlet-kd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Scarlet Rev3+ (SKU-7/Kingdisplay) board device tree source
8 /dts-v1/;
10 #include "rk3399-gru-scarlet.dtsi"
14 compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15",
15 "google,scarlet-rev14-sku7", "google,scarlet-rev14",
16 "google,scarlet-rev13-sku7", "google,scarlet-rev13",
17 "google,scarlet-rev12-sku7", "google,scarlet-rev12",
18 "google,scarlet-rev11-sku7", "google,scarlet-rev11",
19 "google,scarlet-rev10-sku7", "google,scarlet-rev10",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/rockchip/
H A Dpower_domain.txt1 * Rockchip Power Domains
3 Rockchip processors include support for multiple power domains which can be
4 powered up/down by software based on different application scenes to save power.
6 Required properties for power domain controller:
7 - compatible: Should be one of the following.
8 "rockchip,px30-power-controller" - for PX30 SoCs.
9 "rockchip,rk3036-power-controller" - for RK3036 SoCs.
10 "rockchip,rk3066-power-controller" - for RK3066 SoCs.
11 "rockchip,rk3128-power-controller" - for RK3128 SoCs.
12 "rockchip,rk3188-power-controller" - for RK3188 SoCs.
[all …]
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Drockchip,vdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
12 description: |-
13 The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
19 - const: rockchip,rk3399-vdec
20 - items:
21 - enum:
22 - rockchip,rk3228-vdec
[all …]
H A Drockchip-rga.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-rga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jacob Chen <jacob-chen@iotwrt.com>
16 - Ezequiel Garcia <ezequiel@collabora.com>
21 - const: rockchip,rk3288-rga
22 - const: rockchip,rk3399-rga
23 - items:
24 - enum:
[all …]
H A Drockchip-isp1.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
19 - fsl,imx8mp-isp
20 - rockchip,px30-cif-isp
21 - rockchip,rk3399-cif-isp
30 interrupt-names:
32 - const: isp
[all …]
H A Drockchip-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ezequiel Garcia <ezequiel@collabora.com>
19 - enum:
20 - rockchip,rk3036-vpu
21 - rockchip,rk3066-vpu
22 - rockchip,rk3288-vpu
23 - rockchip,rk3328-vpu
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
H A Dphy-rockchip-inno-usb2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
[all …]
H A Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchi
[all...]
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Drockchip,rk3399-dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/
H A Dcdn-dp-rockchip.txt1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
18 to respective power domain.
[all …]
H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chip
[all...]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
[all...]
/freebsd/sys/contrib/device-tree/Bindings/arm/rockchip/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Management Unit (PMU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The PMU is used to turn on and off different power domains of the SoCs.
15 This includes the power to the CPU cores.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
[all …]
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt1 * Rockchip rk3399 DMC (Dynamic Memory Controller) device
4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
15 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
[all …]

1234