| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetMachine.cpp | 1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Implements the info about RISC-V target spec.
11 //===----------------------------------------------------------------------===//
15 #include "RISCV.h"
46 "riscv-enable-copyelim",
52 EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
56 EnableMachineCombiner("riscv-enable-machine-combiner",
61 "riscv-v-vector-bits-max",
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| H A D | RISCVInstrInfo.cpp | 1 //===-- RISCVInstrInfo.cpp - RISC-V Instruction Information -----*
70 namespace llvm::RISCV { global() namespace
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| H A D | RISCVISelLowering.h | 1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
17 #include "RISCV.h"
30 // clang-format off
37 /// Select with condition operator - This selects between a true value and
57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
68 // RV64I shifts, directly matching the semantics of the named RISC-V
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| H A D | RISCVInstrFormats.td | 1 //===-- RISCVInstrFormats.td - RISC-V Instruction Formats --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // description in the RISC-V User-Level ISA specification as closely as
18 // specification describes immediate encoding in terms of bit-slicing
22 // a 21-bit value (where the LSB is always zero), we describe it as an imm20
25 //===----------------------------------------------------------------------===//
29 // definitions must be kept in-sync with RISCVBaseInfo.h.
74 // with the source vector register groups besides the highest-numbered part of
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| H A D | RISCVInstrInfoZfh.td | 1 //===-- RISCVInstrInfoZfh.td - RISC-V 'Zfh' instructions ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions from the standard 'Zfh'
10 // half-precision floating-point extension, version 1.0.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // RISC-V specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
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| H A D | RISCVInstrInfoD.td | 1 //===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions from the standard 'D',
10 // Double-Precision Floating-Point instruction set extension.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // RISC-V specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
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| H A D | RISCVInstrInfoF.td | 1 //===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions from the standard 'F',
10 // Single-Precision Floating-Point instruction set extension.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // RISC-V specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
73 return N->getFlags().hasNoSignedZeros();
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| H A D | RISCVInstrInfo.td | 1 //===-- RISCVInstrInfo.td - Target Description for RISC-V --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions in TableGen format.
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // RISC-V specific DAG Nodes.
15 //===----------------------------------------------------------------------===//
17 // Target-independent type requirements, but with target-specific formats.
23 // Target-dependent type requirements.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 1 //===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains small standalone enum definitions for the RISC-V target
10 // useful for the compiler back-end and the MC libraries.
12 //===----------------------------------------------------------------------===//
28 // RISCVII - This namespace holds all of the target specific flags that
119 // registers and destination registers according to the vector spec.
120 // 0 -> not a vector pseudo
121 // 1 -> default value for vector pseudos. not widening or narrowing.
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| /freebsd/contrib/llvm-project/libunwind/include/ |
| H A D | libunwind.h | 1 //===----------
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| /freebsd/sys/riscv/riscv/ |
| H A D | identcpu.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
63 const char machine[] = "riscv";
75 /* Supervisor-mode extension support. */
84 u_int isa_extensions; /* Single-letter extensions. */
97 * Micro-architecture tables.
104 #define MARCHID_END { -1ul, NULL }
106 /* Open-source RISC-V architecture IDs; globally allocated. */
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| H A D | plic.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * and Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of
52 #include <dt-bindings/interrupt-controller/irq.h>
70 (_sc->contexts[_cpu].enable_offset + ((_irq) / 32) * sizeof(uint32_t))
72 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_THRESHOLD)
74 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_CLAIM)
106 { "riscv,plic0", 1 },
107 { "sifive,plic-1.0.0", 1 },
108 { "thead,c900-plic", 1 },
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| /freebsd/contrib/llvm-project/lld/ELF/Arch/ |
| H A D | RISCV.cpp | 1 //===- RISCV.cpp ----------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
30 class RISCV final : public TargetInfo { class
32 RISCV();
54 // of the psABI spec.
97 // Extract bits v[begin:end], where range is inclusive, and begin must be < 63.
98 static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) { in extractBits() argument
99 return (v & ((1ULL << (begin + 1)) - 1)) >> end; in extractBits()
110 RISCV::RISCV() { in RISCV() function in RISCV
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 1 //===-- RISCVAsmParser.cpp - Parse RISC-V assembly to MCInst instructions -===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
47 #define DEBUG_TYPE "riscv-asm-parser"
50 "Number of RISC-V Compressed instructions emitted");
52 static cl::opt<bool> AddBuildAttributes("riscv-add-build-attributes",
56 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
85 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } in isRV64()
86 bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureStdExtE); } in isRVE()
88 return getSTI().hasFeature(RISCV::Experimental); in enableExperimentalExtension()
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | RISCVISAInfo.cpp | 1 //===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
84 outs() << "All available -march extensions for RISC-V\n\n"; in printSupportedExtensions()
103 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printSupportedExtensions()
114 outs() << "\nUse -march to specify the target's extension.\n" in printSupportedExtensions()
115 "For example, clang -march=rv32i_v1p0\n"; in printSupportedExtensions()
121 outs() << "Extensions enabled for the given RISC-V target\n\n"; in printEnabledExtensions()
141 if (EnabledFeatureNames.count("experimental-" + Name.str()) != 0) { in printEnabledExtensions()
149 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printEnabledExtensions()
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| /freebsd/contrib/llvm-project/clang/lib/AST/ |
| H A D | ItaniumMangle.cpp | 1 //===--- ItaniumMangle.cpp - Itanium C++ Name Mangling ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // ABI-compatible with GCC):
13 // http://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangling
15 //===----------------------------------------------------------------------===//
51 if (const FunctionTemplateDecl *ftd = fn->getPrimaryTemplate()) in getStructor()
52 return ftd->getTemplatedDecl(); in getStructor()
67 return Record->isLambda(); in isLambda()
146 if (Tag->getName().empty() && !Tag->getTypedefNameForAnonDecl()) in getNextDiscriminator()
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| /freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/ |
| H A D | Clang.cpp | 1 //===-- Clang.cpp - Clang+LLVM ToolChain Implementations --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
18 #include "Arch/RISCV.h"
47 #include "llvm/Config/llvm-config.h"
81 << A->getBaseArg().getAsString(Args) in CheckPreprocessingOptions()
82 << (D.IsCLMode() ? "/E, /P or /EP" : "-E"); in CheckPreprocessingOptions()
92 D.Diag(diag::err_drv_argument_not_allowed_with) << A->getAsString(Args) in CheckCodeGenerationOptions()
93 << "-static"; in CheckCodeGenerationOptions()
97 // This is used for the space-separated argument list specified with
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| /freebsd/contrib/llvm-project/lld/ELF/ |
| H A D | Relocations.cpp | 1 //===- Relocations.cpp ----------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains platform-independent functions to process relocations.
28 // - create GOT/PLT entries
29 // - create new relocations in .dynsym to let the dynamic linker resolve
31 // relocations can be resolved at link-time)
32 // - create COPY relocs and reserve space in .bss
33 // - replace expensive relocs (in terms of runtime cost) with cheap ones
34 // - error out infeasible combinations such as PIC and non-relative relocs
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenModule.cpp | 1 //===--- CodeGenModule.cpp - Emit LLVM Code from ASTs for a Module --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This coordinates the per-module state used while generating code.
11 //===----------------------------------------------------------------------===//
84 "limited-coverage-experimental", llvm::cl::Hidden,
150 else if (Target.getABI() == "aapcs-soft") in createTargetCodeGenInfo()
161 if (Target.getABI() == "experimental-mv") in createTargetCodeGenInfo()
175 if (ABIStr == "apcs-gnu") in createTargetCodeGenInfo()
212 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!"); in createTargetCodeGenInfo()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | EmulateInstructionRISCV.cpp | 1 //===-- EmulateInstructionRISCV.cpp ---------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 #include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
47 // funct3 means "3-bits function selector", which RISC-V ISA uses as minor
101 return gpr_x1_riscv + reg_encode - 1; in GPREncodingToLLDB()
226 // Read T from memory, then load its sign-extended value m_emu to register.
349 if (!inst || (!std::holds_alternative<LR_W>(inst->decoded) && in AtomicSequence()
350 !std::holds_alternative<LR_D>(inst->decoded))) in AtomicSequence()
355 if (!inst || !std::holds_alternative<B>(inst->decoded)) in AtomicSequence()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | AttrDocs.td | 1 //==--- AttrDocs.td - Attribute documentation ----------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===---------------------------------------------------------------------===//
9 // To test that the documentation builds cleanly, you must run clang-tblgen to
15 // To run clang-tblgen to generate the .rst file:
16 // clang-tblgen -gen-attr-docs -I <root>/llvm/tools/clang/include
17 // <root>/llvm/tools/clang/include/clang/Basic/Attr.td -o
20 // To run sphinx to generate the .html files (note that sphinx-build must be
24 // Non-Windows (from within the clang\docs directory):
25 // sphinx-build -b html _build/html
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 1 //===- ValueTracking.cpp - Walk computations to compute properties --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
88 static cl::opt<unsigned> DomConditionsMaxUses("dom-conditions-max-uses",
95 if (unsigned BitWidth = Ty->getScalarSizeInBits()) in getBitWidth()
103 static const Instruction *safeCxtI(const Value *V, const Instruction *CxtI) { in safeCxtI() argument
106 if (CxtI && CxtI->getParent()) in safeCxtI()
109 // If the value is really an already-inserted instruction, then use that. in safeCxtI()
110 CxtI = dyn_cast<Instruction>(V); in safeCxtI()
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaDeclAttr.cpp | 1 //===--- SemaDeclAttr.cpp - Declaration Attribute Handling ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements decl-related attribute processing.
11 //===----------------------------------------------------------------------===//
105 S.Diag(Expr->getExprLoc(), diag::err_ice_too_large) in checkPositiveIntArgument()
117 const auto *Literal = dyn_cast<StringLiteral>(E->IgnoreParenCasts()); in checkStringLiteralArgumentAttr()
119 *ArgLocation = E->getBeginLoc(); in checkStringLiteralArgumentAttr()
121 if (!Literal || (!Literal->isUnevaluated() && !Literal->isOrdinary())) { in checkStringLiteralArgumentAttr()
122 Diag(E->getBeginLoc(), diag::err_attribute_argument_type) in checkStringLiteralArgumentAttr()
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